Macro name | Arguments | Value |
__XC | none | 1 |
__XC8 | none | 1 |
_MPC_ | none | 1 |
_PIC18 | none | 1 |
_18F8720 | none | 1 |
__XC__ | none | 1 |
__STACK | none | __STACK_COMPILED |
__18F8720 | none | 1 |
__XC8__ | none | 1 |
_RAMSIZE | none | 3840 |
_COMMON_ | none | 1 |
_ROMSIZE | none | 131072 |
__EXTMEM | none | 1966080 |
__DATE__ | none | "Oct 03 2017" |
__FILE__ | none | dynamic replacement |
__LINE__ | none | dynamic replacement |
__STDC__ | none | 1 |
__TIME__ | none | "14:30:43" |
HI_TECH_C | none | 1 |
__18F8720__ | none | 1 |
__PICC18__ | none | 1 |
_EEPROMSIZE | none | 1024 |
_OMNI_CODE_ | none | 1 |
__OPTIM_ASM | none | 0x1 |
__OPTIM_NONE | none | 0x0 |
__OPTIM_SIZE | none | 0x40000 |
_COMMON_ADDR_ | none | 0 |
_HTC_EDITION_ | none | 0 |
__OPTIM_DEBUG | none | 0x80000 |
__OPTIM_LOCAL | none | 0x200000 |
_ERRATA_TYPES | none | 120 |
__OPTIM_SPACE | none | 0x40000 |
__OPTIM_FLAGS | none | 0x0 |
__XC8_VERSION | none | 1440 |
__OPTIM_SPEED | none | 0x20000 |
_COMMON_SIZE_ | none | 96 |
__STACK_HYBRID | none | 2 |
_HTC_VER_PLVL_ | none | 0 |
_18FXX20_FAMILY_ | none | 1 |
__OPTIM_ASMFILE | none | 0x2 |
_HTC_VER_PATCH_ | none | 48 |
_HTC_VER_MAJOR_ | none | 10 |
_HTC_VER_MINOR_ | none | 44 |
__STACK_COMPILED | none | 1 |
__TRADITIONAL18__ | none | 1 |
_FLASH_ERASE_SIZE | none | 64 |
__STACK_REENTRANT | none | 4 |
_FLASH_WRITE_SIZE | none | 8 |
__OPTIMIZE_NONE__ | none | 1 |
XPRJ_neoptimalizovano | none | neoptimalizovano |
__PIC18F8720A__ | none | |
_XC_H_ | none | |
_HTC_H_ | none | |
_CCI_H_ | none | |
___AT_H_ | none | |
__at | 1 | __attribute__((address(<0>))) |
___mkstr1 | 1 | <0> |
___mkstr | 1 | ___mkstr1(<0>) |
__deprecate | none | __attribute__((deprecated)) |
__cp0 | 1 | __attribute__((unsupported("the __cp0() construct is not supported by this architecture"))) |
__cp0 | empty | __attribute__((unsupported("the __cp0() construct is not supported by this architecture"))) |
__abi | 1 | __attribute__((unsupported("the __abi() construct is not supported by this architecture"))) |
__abi | empty | __attribute__((unsupported("the __abi() construct is not supported by this architecture"))) |
__align | empty | __attribute__((unsupported("the __align() attribute is not used by this compiler"))) |
__align | 1 | __attribute__((unsupported("the __align() attribute is not used by this compiler"))) |
__xdata | none | __attribute__((unsupported("__xdata is not defined on this architecture"))) |
__ydata | none | __attribute__((unsupported("__ydata in not defined on this architecture"))) |
__bank | 1 | __attribute__((unsupported("__bank() is not presently supported by this architecture and will be ignored"))) |
__LITE__ | none | 0 |
__STD__ | none | 1 |
__PRO__ | none | 2 |
___mkstr1 | 1 | <0> |
___mkstr | 1 | ___mkstr1(<0>) |
_OMNITARGET | none | ((void *)0xFFFFFFFF) |
_XC8DEBUG_H_ | none | |
_ABORT_MACRO_ | none | |
abort | empty | exit(-1) |
RESET | empty | asm("reset") |
__debug_break | empty | ((void)0) |
_EXIT_MACRO_ | none | |
exit | 1 | do { __debug_break(); RESET(); }while(0) |
_PIC18_H | none | |
_PIC18_CHIP_SELECT_H_ | none | |
_HEADER_NOT_FOUND | none | |
_PIC18F8720_H_ | none | |
RCSTA2 | none | <\077435>RCSTA2 |
RCSTA2 | none | <\077435>RCSTA2 |
_RCSTA2_RX9D_POSN | none | 0x0 |
_RCSTA2_RX9D_POSITION | none | 0x0 |
_RCSTA2_RX9D_SIZE | none | 0x1 |
_RCSTA2_RX9D_LENGTH | none | 0x1 |
_RCSTA2_RX9D_MASK | none | 0x1 |
_RCSTA2_OERR_POSN | none | 0x1 |
_RCSTA2_OERR_POSITION | none | 0x1 |
_RCSTA2_OERR_SIZE | none | 0x1 |
_RCSTA2_OERR_LENGTH | none | 0x1 |
_RCSTA2_OERR_MASK | none | 0x2 |
_RCSTA2_FERR_POSN | none | 0x2 |
_RCSTA2_FERR_POSITION | none | 0x2 |
_RCSTA2_FERR_SIZE | none | 0x1 |
_RCSTA2_FERR_LENGTH | none | 0x1 |
_RCSTA2_FERR_MASK | none | 0x4 |
_RCSTA2_ADDEN_POSN | none | 0x3 |
_RCSTA2_ADDEN_POSITION | none | 0x3 |
_RCSTA2_ADDEN_SIZE | none | 0x1 |
_RCSTA2_ADDEN_LENGTH | none | 0x1 |
_RCSTA2_ADDEN_MASK | none | 0x8 |
_RCSTA2_CREN_POSN | none | 0x4 |
_RCSTA2_CREN_POSITION | none | 0x4 |
_RCSTA2_CREN_SIZE | none | 0x1 |
_RCSTA2_CREN_LENGTH | none | 0x1 |
_RCSTA2_CREN_MASK | none | 0x10 |
_RCSTA2_SREN_POSN | none | 0x5 |
_RCSTA2_SREN_POSITION | none | 0x5 |
_RCSTA2_SREN_SIZE | none | 0x1 |
_RCSTA2_SREN_LENGTH | none | 0x1 |
_RCSTA2_SREN_MASK | none | 0x20 |
_RCSTA2_RX9_POSN | none | 0x6 |
_RCSTA2_RX9_POSITION | none | 0x6 |
_RCSTA2_RX9_SIZE | none | 0x1 |
_RCSTA2_RX9_LENGTH | none | 0x1 |
_RCSTA2_RX9_MASK | none | 0x40 |
_RCSTA2_SPEN_POSN | none | 0x7 |
_RCSTA2_SPEN_POSITION | none | 0x7 |
_RCSTA2_SPEN_SIZE | none | 0x1 |
_RCSTA2_SPEN_LENGTH | none | 0x1 |
_RCSTA2_SPEN_MASK | none | 0x80 |
_RCSTA2_RCD8_POSN | none | 0x0 |
_RCSTA2_RCD8_POSITION | none | 0x0 |
_RCSTA2_RCD8_SIZE | none | 0x1 |
_RCSTA2_RCD8_LENGTH | none | 0x1 |
_RCSTA2_RCD8_MASK | none | 0x1 |
_RCSTA2_ADEN_POSN | none | 0x3 |
_RCSTA2_ADEN_POSITION | none | 0x3 |
_RCSTA2_ADEN_SIZE | none | 0x1 |
_RCSTA2_ADEN_LENGTH | none | 0x1 |
_RCSTA2_ADEN_MASK | none | 0x8 |
_RCSTA2_RC9_POSN | none | 0x6 |
_RCSTA2_RC9_POSITION | none | 0x6 |
_RCSTA2_RC9_SIZE | none | 0x1 |
_RCSTA2_RC9_LENGTH | none | 0x1 |
_RCSTA2_RC9_MASK | none | 0x40 |
_RCSTA2_NOT_RC8_POSN | none | 0x6 |
_RCSTA2_NOT_RC8_POSITION | none | 0x6 |
_RCSTA2_NOT_RC8_SIZE | none | 0x1 |
_RCSTA2_NOT_RC8_LENGTH | none | 0x1 |
_RCSTA2_NOT_RC8_MASK | none | 0x40 |
_RCSTA2_nRC8_POSN | none | 0x6 |
_RCSTA2_nRC8_POSITION | none | 0x6 |
_RCSTA2_nRC8_SIZE | none | 0x1 |
_RCSTA2_nRC8_LENGTH | none | 0x1 |
_RCSTA2_nRC8_MASK | none | 0x40 |
_RCSTA2_RC8_9_POSN | none | 0x6 |
_RCSTA2_RC8_9_POSITION | none | 0x6 |
_RCSTA2_RC8_9_SIZE | none | 0x1 |
_RCSTA2_RC8_9_LENGTH | none | 0x1 |
_RCSTA2_RC8_9_MASK | none | 0x40 |
_RCSTA2_RX9D2_POSN | none | 0x0 |
_RCSTA2_RX9D2_POSITION | none | 0x0 |
_RCSTA2_RX9D2_SIZE | none | 0x1 |
_RCSTA2_RX9D2_LENGTH | none | 0x1 |
_RCSTA2_RX9D2_MASK | none | 0x1 |
_RCSTA2_OERR2_POSN | none | 0x1 |
_RCSTA2_OERR2_POSITION | none | 0x1 |
_RCSTA2_OERR2_SIZE | none | 0x1 |
_RCSTA2_OERR2_LENGTH | none | 0x1 |
_RCSTA2_OERR2_MASK | none | 0x2 |
_RCSTA2_FERR2_POSN | none | 0x2 |
_RCSTA2_FERR2_POSITION | none | 0x2 |
_RCSTA2_FERR2_SIZE | none | 0x1 |
_RCSTA2_FERR2_LENGTH | none | 0x1 |
_RCSTA2_FERR2_MASK | none | 0x4 |
_RCSTA2_ADDEN2_POSN | none | 0x3 |
_RCSTA2_ADDEN2_POSITION | none | 0x3 |
_RCSTA2_ADDEN2_SIZE | none | 0x1 |
_RCSTA2_ADDEN2_LENGTH | none | 0x1 |
_RCSTA2_ADDEN2_MASK | none | 0x8 |
_RCSTA2_CREN2_POSN | none | 0x4 |
_RCSTA2_CREN2_POSITION | none | 0x4 |
_RCSTA2_CREN2_SIZE | none | 0x1 |
_RCSTA2_CREN2_LENGTH | none | 0x1 |
_RCSTA2_CREN2_MASK | none | 0x10 |
_RCSTA2_SREN2_POSN | none | 0x5 |
_RCSTA2_SREN2_POSITION | none | 0x5 |
_RCSTA2_SREN2_SIZE | none | 0x1 |
_RCSTA2_SREN2_LENGTH | none | 0x1 |
_RCSTA2_SREN2_MASK | none | 0x20 |
_RCSTA2_RX92_POSN | none | 0x6 |
_RCSTA2_RX92_POSITION | none | 0x6 |
_RCSTA2_RX92_SIZE | none | 0x1 |
_RCSTA2_RX92_LENGTH | none | 0x1 |
_RCSTA2_RX92_MASK | none | 0x40 |
_RCSTA2_SPEN2_POSN | none | 0x7 |
_RCSTA2_SPEN2_POSITION | none | 0x7 |
_RCSTA2_SPEN2_SIZE | none | 0x1 |
_RCSTA2_SPEN2_LENGTH | none | 0x1 |
_RCSTA2_SPEN2_MASK | none | 0x80 |
_RCSTA2_RCD82_POSN | none | 0x0 |
_RCSTA2_RCD82_POSITION | none | 0x0 |
_RCSTA2_RCD82_SIZE | none | 0x1 |
_RCSTA2_RCD82_LENGTH | none | 0x1 |
_RCSTA2_RCD82_MASK | none | 0x1 |
_RCSTA2_RC8_92_POSN | none | 0x6 |
_RCSTA2_RC8_92_POSITION | none | 0x6 |
_RCSTA2_RC8_92_SIZE | none | 0x1 |
_RCSTA2_RC8_92_LENGTH | none | 0x1 |
_RCSTA2_RC8_92_MASK | none | 0x40 |
_RCSTA2_RC92_POSN | none | 0x6 |
_RCSTA2_RC92_POSITION | none | 0x6 |
_RCSTA2_RC92_SIZE | none | 0x1 |
_RCSTA2_RC92_LENGTH | none | 0x1 |
_RCSTA2_RC92_MASK | none | 0x40 |
TXSTA2 | none | <\077435>TXSTA2 |
TXSTA2 | none | <\077435>TXSTA2 |
_TXSTA2_TX9D_POSN | none | 0x0 |
_TXSTA2_TX9D_POSITION | none | 0x0 |
_TXSTA2_TX9D_SIZE | none | 0x1 |
_TXSTA2_TX9D_LENGTH | none | 0x1 |
_TXSTA2_TX9D_MASK | none | 0x1 |
_TXSTA2_TRMT_POSN | none | 0x1 |
_TXSTA2_TRMT_POSITION | none | 0x1 |
_TXSTA2_TRMT_SIZE | none | 0x1 |
_TXSTA2_TRMT_LENGTH | none | 0x1 |
_TXSTA2_TRMT_MASK | none | 0x2 |
_TXSTA2_BRGH_POSN | none | 0x2 |
_TXSTA2_BRGH_POSITION | none | 0x2 |
_TXSTA2_BRGH_SIZE | none | 0x1 |
_TXSTA2_BRGH_LENGTH | none | 0x1 |
_TXSTA2_BRGH_MASK | none | 0x4 |
_TXSTA2_SYNC_POSN | none | 0x4 |
_TXSTA2_SYNC_POSITION | none | 0x4 |
_TXSTA2_SYNC_SIZE | none | 0x1 |
_TXSTA2_SYNC_LENGTH | none | 0x1 |
_TXSTA2_SYNC_MASK | none | 0x10 |
_TXSTA2_TXEN_POSN | none | 0x5 |
_TXSTA2_TXEN_POSITION | none | 0x5 |
_TXSTA2_TXEN_SIZE | none | 0x1 |
_TXSTA2_TXEN_LENGTH | none | 0x1 |
_TXSTA2_TXEN_MASK | none | 0x20 |
_TXSTA2_TX9_POSN | none | 0x6 |
_TXSTA2_TX9_POSITION | none | 0x6 |
_TXSTA2_TX9_SIZE | none | 0x1 |
_TXSTA2_TX9_LENGTH | none | 0x1 |
_TXSTA2_TX9_MASK | none | 0x40 |
_TXSTA2_CSRC_POSN | none | 0x7 |
_TXSTA2_CSRC_POSITION | none | 0x7 |
_TXSTA2_CSRC_SIZE | none | 0x1 |
_TXSTA2_CSRC_LENGTH | none | 0x1 |
_TXSTA2_CSRC_MASK | none | 0x80 |
_TXSTA2_TXD8_POSN | none | 0x0 |
_TXSTA2_TXD8_POSITION | none | 0x0 |
_TXSTA2_TXD8_SIZE | none | 0x1 |
_TXSTA2_TXD8_LENGTH | none | 0x1 |
_TXSTA2_TXD8_MASK | none | 0x1 |
_TXSTA2_TX8_9_POSN | none | 0x6 |
_TXSTA2_TX8_9_POSITION | none | 0x6 |
_TXSTA2_TX8_9_SIZE | none | 0x1 |
_TXSTA2_TX8_9_LENGTH | none | 0x1 |
_TXSTA2_TX8_9_MASK | none | 0x40 |
_TXSTA2_NOT_TX8_POSN | none | 0x6 |
_TXSTA2_NOT_TX8_POSITION | none | 0x6 |
_TXSTA2_NOT_TX8_SIZE | none | 0x1 |
_TXSTA2_NOT_TX8_LENGTH | none | 0x1 |
_TXSTA2_NOT_TX8_MASK | none | 0x40 |
_TXSTA2_nTX8_POSN | none | 0x6 |
_TXSTA2_nTX8_POSITION | none | 0x6 |
_TXSTA2_nTX8_SIZE | none | 0x1 |
_TXSTA2_nTX8_LENGTH | none | 0x1 |
_TXSTA2_nTX8_MASK | none | 0x40 |
_TXSTA2_TX9D2_POSN | none | 0x0 |
_TXSTA2_TX9D2_POSITION | none | 0x0 |
_TXSTA2_TX9D2_SIZE | none | 0x1 |
_TXSTA2_TX9D2_LENGTH | none | 0x1 |
_TXSTA2_TX9D2_MASK | none | 0x1 |
_TXSTA2_TRMT2_POSN | none | 0x1 |
_TXSTA2_TRMT2_POSITION | none | 0x1 |
_TXSTA2_TRMT2_SIZE | none | 0x1 |
_TXSTA2_TRMT2_LENGTH | none | 0x1 |
_TXSTA2_TRMT2_MASK | none | 0x2 |
_TXSTA2_BRGH2_POSN | none | 0x2 |
_TXSTA2_BRGH2_POSITION | none | 0x2 |
_TXSTA2_BRGH2_SIZE | none | 0x1 |
_TXSTA2_BRGH2_LENGTH | none | 0x1 |
_TXSTA2_BRGH2_MASK | none | 0x4 |
_TXSTA2_SENDB2_POSN | none | 0x3 |
_TXSTA2_SENDB2_POSITION | none | 0x3 |
_TXSTA2_SENDB2_SIZE | none | 0x1 |
_TXSTA2_SENDB2_LENGTH | none | 0x1 |
_TXSTA2_SENDB2_MASK | none | 0x8 |
_TXSTA2_SYNC2_POSN | none | 0x4 |
_TXSTA2_SYNC2_POSITION | none | 0x4 |
_TXSTA2_SYNC2_SIZE | none | 0x1 |
_TXSTA2_SYNC2_LENGTH | none | 0x1 |
_TXSTA2_SYNC2_MASK | none | 0x10 |
_TXSTA2_TXEN2_POSN | none | 0x5 |
_TXSTA2_TXEN2_POSITION | none | 0x5 |
_TXSTA2_TXEN2_SIZE | none | 0x1 |
_TXSTA2_TXEN2_LENGTH | none | 0x1 |
_TXSTA2_TXEN2_MASK | none | 0x20 |
_TXSTA2_TX92_POSN | none | 0x6 |
_TXSTA2_TX92_POSITION | none | 0x6 |
_TXSTA2_TX92_SIZE | none | 0x1 |
_TXSTA2_TX92_LENGTH | none | 0x1 |
_TXSTA2_TX92_MASK | none | 0x40 |
_TXSTA2_CSRC2_POSN | none | 0x7 |
_TXSTA2_CSRC2_POSITION | none | 0x7 |
_TXSTA2_CSRC2_SIZE | none | 0x1 |
_TXSTA2_CSRC2_LENGTH | none | 0x1 |
_TXSTA2_CSRC2_MASK | none | 0x80 |
_TXSTA2_TXD82_POSN | none | 0x0 |
_TXSTA2_TXD82_POSITION | none | 0x0 |
_TXSTA2_TXD82_SIZE | none | 0x1 |
_TXSTA2_TXD82_LENGTH | none | 0x1 |
_TXSTA2_TXD82_MASK | none | 0x1 |
_TXSTA2_TX8_92_POSN | none | 0x6 |
_TXSTA2_TX8_92_POSITION | none | 0x6 |
_TXSTA2_TX8_92_SIZE | none | 0x1 |
_TXSTA2_TX8_92_LENGTH | none | 0x1 |
_TXSTA2_TX8_92_MASK | none | 0x40 |
TXREG2 | none | <\077435>TXREG2 |
TXREG2 | none | <\077435>TXREG2 |
RCREG2 | none | <\077435>RCREG2 |
RCREG2 | none | <\077435>RCREG2 |
SPBRG2 | none | <\077435>SPBRG2 |
SPBRG2 | none | <\077435>SPBRG2 |
CCP5CON | none | <\077435>CCP5CON |
CCP5CON | none | <\077435>CCP5CON |
_CCP5CON_CCP5M_POSN | none | 0x0 |
_CCP5CON_CCP5M_POSITION | none | 0x0 |
_CCP5CON_CCP5M_SIZE | none | 0x4 |
_CCP5CON_CCP5M_LENGTH | none | 0x4 |
_CCP5CON_CCP5M_MASK | none | 0xF |
_CCP5CON_DC5B_POSN | none | 0x4 |
_CCP5CON_DC5B_POSITION | none | 0x4 |
_CCP5CON_DC5B_SIZE | none | 0x2 |
_CCP5CON_DC5B_LENGTH | none | 0x2 |
_CCP5CON_DC5B_MASK | none | 0x30 |
_CCP5CON_CCP5M0_POSN | none | 0x0 |
_CCP5CON_CCP5M0_POSITION | none | 0x0 |
_CCP5CON_CCP5M0_SIZE | none | 0x1 |
_CCP5CON_CCP5M0_LENGTH | none | 0x1 |
_CCP5CON_CCP5M0_MASK | none | 0x1 |
_CCP5CON_CCP5M1_POSN | none | 0x1 |
_CCP5CON_CCP5M1_POSITION | none | 0x1 |
_CCP5CON_CCP5M1_SIZE | none | 0x1 |
_CCP5CON_CCP5M1_LENGTH | none | 0x1 |
_CCP5CON_CCP5M1_MASK | none | 0x2 |
_CCP5CON_CCP5M2_POSN | none | 0x2 |
_CCP5CON_CCP5M2_POSITION | none | 0x2 |
_CCP5CON_CCP5M2_SIZE | none | 0x1 |
_CCP5CON_CCP5M2_LENGTH | none | 0x1 |
_CCP5CON_CCP5M2_MASK | none | 0x4 |
_CCP5CON_CCP5M3_POSN | none | 0x3 |
_CCP5CON_CCP5M3_POSITION | none | 0x3 |
_CCP5CON_CCP5M3_SIZE | none | 0x1 |
_CCP5CON_CCP5M3_LENGTH | none | 0x1 |
_CCP5CON_CCP5M3_MASK | none | 0x8 |
_CCP5CON_DC5B0_POSN | none | 0x4 |
_CCP5CON_DC5B0_POSITION | none | 0x4 |
_CCP5CON_DC5B0_SIZE | none | 0x1 |
_CCP5CON_DC5B0_LENGTH | none | 0x1 |
_CCP5CON_DC5B0_MASK | none | 0x10 |
_CCP5CON_DC5B1_POSN | none | 0x5 |
_CCP5CON_DC5B1_POSITION | none | 0x5 |
_CCP5CON_DC5B1_SIZE | none | 0x1 |
_CCP5CON_DC5B1_LENGTH | none | 0x1 |
_CCP5CON_DC5B1_MASK | none | 0x20 |
_CCP5CON_DCCP5Y_POSN | none | 0x4 |
_CCP5CON_DCCP5Y_POSITION | none | 0x4 |
_CCP5CON_DCCP5Y_SIZE | none | 0x1 |
_CCP5CON_DCCP5Y_LENGTH | none | 0x1 |
_CCP5CON_DCCP5Y_MASK | none | 0x10 |
_CCP5CON_DCCP5X_POSN | none | 0x5 |
_CCP5CON_DCCP5X_POSITION | none | 0x5 |
_CCP5CON_DCCP5X_SIZE | none | 0x1 |
_CCP5CON_DCCP5X_LENGTH | none | 0x1 |
_CCP5CON_DCCP5X_MASK | none | 0x20 |
CCPR5 | none | <\077435>CCPR5 |
CCPR5 | none | <\077435>CCPR5 |
CCPR5L | none | <\077435>CCPR5L |
CCPR5L | none | <\077435>CCPR5L |
CCPR5H | none | <\077435>CCPR5H |
CCPR5H | none | <\077435>CCPR5H |
CCP4CON | none | <\077435>CCP4CON |
CCP4CON | none | <\077435>CCP4CON |
_CCP4CON_CCP4M_POSN | none | 0x0 |
_CCP4CON_CCP4M_POSITION | none | 0x0 |
_CCP4CON_CCP4M_SIZE | none | 0x4 |
_CCP4CON_CCP4M_LENGTH | none | 0x4 |
_CCP4CON_CCP4M_MASK | none | 0xF |
_CCP4CON_DC4B_POSN | none | 0x4 |
_CCP4CON_DC4B_POSITION | none | 0x4 |
_CCP4CON_DC4B_SIZE | none | 0x2 |
_CCP4CON_DC4B_LENGTH | none | 0x2 |
_CCP4CON_DC4B_MASK | none | 0x30 |
_CCP4CON_CCP4M0_POSN | none | 0x0 |
_CCP4CON_CCP4M0_POSITION | none | 0x0 |
_CCP4CON_CCP4M0_SIZE | none | 0x1 |
_CCP4CON_CCP4M0_LENGTH | none | 0x1 |
_CCP4CON_CCP4M0_MASK | none | 0x1 |
_CCP4CON_CCP4M1_POSN | none | 0x1 |
_CCP4CON_CCP4M1_POSITION | none | 0x1 |
_CCP4CON_CCP4M1_SIZE | none | 0x1 |
_CCP4CON_CCP4M1_LENGTH | none | 0x1 |
_CCP4CON_CCP4M1_MASK | none | 0x2 |
_CCP4CON_CCP4M2_POSN | none | 0x2 |
_CCP4CON_CCP4M2_POSITION | none | 0x2 |
_CCP4CON_CCP4M2_SIZE | none | 0x1 |
_CCP4CON_CCP4M2_LENGTH | none | 0x1 |
_CCP4CON_CCP4M2_MASK | none | 0x4 |
_CCP4CON_CCP4M3_POSN | none | 0x3 |
_CCP4CON_CCP4M3_POSITION | none | 0x3 |
_CCP4CON_CCP4M3_SIZE | none | 0x1 |
_CCP4CON_CCP4M3_LENGTH | none | 0x1 |
_CCP4CON_CCP4M3_MASK | none | 0x8 |
_CCP4CON_DC4B0_POSN | none | 0x4 |
_CCP4CON_DC4B0_POSITION | none | 0x4 |
_CCP4CON_DC4B0_SIZE | none | 0x1 |
_CCP4CON_DC4B0_LENGTH | none | 0x1 |
_CCP4CON_DC4B0_MASK | none | 0x10 |
_CCP4CON_DC4B1_POSN | none | 0x5 |
_CCP4CON_DC4B1_POSITION | none | 0x5 |
_CCP4CON_DC4B1_SIZE | none | 0x1 |
_CCP4CON_DC4B1_LENGTH | none | 0x1 |
_CCP4CON_DC4B1_MASK | none | 0x20 |
_CCP4CON_DCCP4Y_POSN | none | 0x4 |
_CCP4CON_DCCP4Y_POSITION | none | 0x4 |
_CCP4CON_DCCP4Y_SIZE | none | 0x1 |
_CCP4CON_DCCP4Y_LENGTH | none | 0x1 |
_CCP4CON_DCCP4Y_MASK | none | 0x10 |
_CCP4CON_DCCP4X_POSN | none | 0x5 |
_CCP4CON_DCCP4X_POSITION | none | 0x5 |
_CCP4CON_DCCP4X_SIZE | none | 0x1 |
_CCP4CON_DCCP4X_LENGTH | none | 0x1 |
_CCP4CON_DCCP4X_MASK | none | 0x20 |
CCPR4 | none | <\077435>CCPR4 |
CCPR4 | none | <\077435>CCPR4 |
CCPR4L | none | <\077435>CCPR4L |
CCPR4L | none | <\077435>CCPR4L |
CCPR4H | none | <\077435>CCPR4H |
CCPR4H | none | <\077435>CCPR4H |
T4CON | none | <\077435>T4CON |
T4CON | none | <\077435>T4CON |
_T4CON_T4CKPS_POSN | none | 0x0 |
_T4CON_T4CKPS_POSITION | none | 0x0 |
_T4CON_T4CKPS_SIZE | none | 0x2 |
_T4CON_T4CKPS_LENGTH | none | 0x2 |
_T4CON_T4CKPS_MASK | none | 0x3 |
_T4CON_TMR4ON_POSN | none | 0x2 |
_T4CON_TMR4ON_POSITION | none | 0x2 |
_T4CON_TMR4ON_SIZE | none | 0x1 |
_T4CON_TMR4ON_LENGTH | none | 0x1 |
_T4CON_TMR4ON_MASK | none | 0x4 |
_T4CON_T4OUTPS_POSN | none | 0x3 |
_T4CON_T4OUTPS_POSITION | none | 0x3 |
_T4CON_T4OUTPS_SIZE | none | 0x4 |
_T4CON_T4OUTPS_LENGTH | none | 0x4 |
_T4CON_T4OUTPS_MASK | none | 0x78 |
_T4CON_T4CKPS0_POSN | none | 0x0 |
_T4CON_T4CKPS0_POSITION | none | 0x0 |
_T4CON_T4CKPS0_SIZE | none | 0x1 |
_T4CON_T4CKPS0_LENGTH | none | 0x1 |
_T4CON_T4CKPS0_MASK | none | 0x1 |
_T4CON_T4CKPS1_POSN | none | 0x1 |
_T4CON_T4CKPS1_POSITION | none | 0x1 |
_T4CON_T4CKPS1_SIZE | none | 0x1 |
_T4CON_T4CKPS1_LENGTH | none | 0x1 |
_T4CON_T4CKPS1_MASK | none | 0x2 |
_T4CON_T4OUTPS0_POSN | none | 0x3 |
_T4CON_T4OUTPS0_POSITION | none | 0x3 |
_T4CON_T4OUTPS0_SIZE | none | 0x1 |
_T4CON_T4OUTPS0_LENGTH | none | 0x1 |
_T4CON_T4OUTPS0_MASK | none | 0x8 |
_T4CON_T4OUTPS1_POSN | none | 0x4 |
_T4CON_T4OUTPS1_POSITION | none | 0x4 |
_T4CON_T4OUTPS1_SIZE | none | 0x1 |
_T4CON_T4OUTPS1_LENGTH | none | 0x1 |
_T4CON_T4OUTPS1_MASK | none | 0x10 |
_T4CON_T4OUTPS2_POSN | none | 0x5 |
_T4CON_T4OUTPS2_POSITION | none | 0x5 |
_T4CON_T4OUTPS2_SIZE | none | 0x1 |
_T4CON_T4OUTPS2_LENGTH | none | 0x1 |
_T4CON_T4OUTPS2_MASK | none | 0x20 |
_T4CON_T4OUTPS3_POSN | none | 0x6 |
_T4CON_T4OUTPS3_POSITION | none | 0x6 |
_T4CON_T4OUTPS3_SIZE | none | 0x1 |
_T4CON_T4OUTPS3_LENGTH | none | 0x1 |
_T4CON_T4OUTPS3_MASK | none | 0x40 |
PR4 | none | <\077435>PR4 |
PR4 | none | <\077435>PR4 |
TMR4 | none | <\077435>TMR4 |
TMR4 | none | <\077435>TMR4 |
PORTA | none | <\077435>PORTA |
PORTA | none | <\077435>PORTA |
_PORTA_RA0_POSN | none | 0x0 |
_PORTA_RA0_POSITION | none | 0x0 |
_PORTA_RA0_SIZE | none | 0x1 |
_PORTA_RA0_LENGTH | none | 0x1 |
_PORTA_RA0_MASK | none | 0x1 |
_PORTA_RA1_POSN | none | 0x1 |
_PORTA_RA1_POSITION | none | 0x1 |
_PORTA_RA1_SIZE | none | 0x1 |
_PORTA_RA1_LENGTH | none | 0x1 |
_PORTA_RA1_MASK | none | 0x2 |
_PORTA_RA2_POSN | none | 0x2 |
_PORTA_RA2_POSITION | none | 0x2 |
_PORTA_RA2_SIZE | none | 0x1 |
_PORTA_RA2_LENGTH | none | 0x1 |
_PORTA_RA2_MASK | none | 0x4 |
_PORTA_RA3_POSN | none | 0x3 |
_PORTA_RA3_POSITION | none | 0x3 |
_PORTA_RA3_SIZE | none | 0x1 |
_PORTA_RA3_LENGTH | none | 0x1 |
_PORTA_RA3_MASK | none | 0x8 |
_PORTA_RA4_POSN | none | 0x4 |
_PORTA_RA4_POSITION | none | 0x4 |
_PORTA_RA4_SIZE | none | 0x1 |
_PORTA_RA4_LENGTH | none | 0x1 |
_PORTA_RA4_MASK | none | 0x10 |
_PORTA_RA5_POSN | none | 0x5 |
_PORTA_RA5_POSITION | none | 0x5 |
_PORTA_RA5_SIZE | none | 0x1 |
_PORTA_RA5_LENGTH | none | 0x1 |
_PORTA_RA5_MASK | none | 0x20 |
_PORTA_RA6_POSN | none | 0x6 |
_PORTA_RA6_POSITION | none | 0x6 |
_PORTA_RA6_SIZE | none | 0x1 |
_PORTA_RA6_LENGTH | none | 0x1 |
_PORTA_RA6_MASK | none | 0x40 |
_PORTA_AN0_POSN | none | 0x0 |
_PORTA_AN0_POSITION | none | 0x0 |
_PORTA_AN0_SIZE | none | 0x1 |
_PORTA_AN0_LENGTH | none | 0x1 |
_PORTA_AN0_MASK | none | 0x1 |
_PORTA_AN1_POSN | none | 0x1 |
_PORTA_AN1_POSITION | none | 0x1 |
_PORTA_AN1_SIZE | none | 0x1 |
_PORTA_AN1_LENGTH | none | 0x1 |
_PORTA_AN1_MASK | none | 0x2 |
_PORTA_AN2_POSN | none | 0x2 |
_PORTA_AN2_POSITION | none | 0x2 |
_PORTA_AN2_SIZE | none | 0x1 |
_PORTA_AN2_LENGTH | none | 0x1 |
_PORTA_AN2_MASK | none | 0x4 |
_PORTA_AN3_POSN | none | 0x3 |
_PORTA_AN3_POSITION | none | 0x3 |
_PORTA_AN3_SIZE | none | 0x1 |
_PORTA_AN3_LENGTH | none | 0x1 |
_PORTA_AN3_MASK | none | 0x8 |
_PORTA_T0CKI_POSN | none | 0x4 |
_PORTA_T0CKI_POSITION | none | 0x4 |
_PORTA_T0CKI_SIZE | none | 0x1 |
_PORTA_T0CKI_LENGTH | none | 0x1 |
_PORTA_T0CKI_MASK | none | 0x10 |
_PORTA_AN4_POSN | none | 0x5 |
_PORTA_AN4_POSITION | none | 0x5 |
_PORTA_AN4_SIZE | none | 0x1 |
_PORTA_AN4_LENGTH | none | 0x1 |
_PORTA_AN4_MASK | none | 0x20 |
_PORTA_OSC2_POSN | none | 0x6 |
_PORTA_OSC2_POSITION | none | 0x6 |
_PORTA_OSC2_SIZE | none | 0x1 |
_PORTA_OSC2_LENGTH | none | 0x1 |
_PORTA_OSC2_MASK | none | 0x40 |
_PORTA_VREFM_POSN | none | 0x2 |
_PORTA_VREFM_POSITION | none | 0x2 |
_PORTA_VREFM_SIZE | none | 0x1 |
_PORTA_VREFM_LENGTH | none | 0x1 |
_PORTA_VREFM_MASK | none | 0x4 |
_PORTA_VREFP_POSN | none | 0x3 |
_PORTA_VREFP_POSITION | none | 0x3 |
_PORTA_VREFP_SIZE | none | 0x1 |
_PORTA_VREFP_LENGTH | none | 0x1 |
_PORTA_VREFP_MASK | none | 0x8 |
_PORTA_LVDIN_POSN | none | 0x5 |
_PORTA_LVDIN_POSITION | none | 0x5 |
_PORTA_LVDIN_SIZE | none | 0x1 |
_PORTA_LVDIN_LENGTH | none | 0x1 |
_PORTA_LVDIN_MASK | none | 0x20 |
_PORTA_CLKO_POSN | none | 0x6 |
_PORTA_CLKO_POSITION | none | 0x6 |
_PORTA_CLKO_SIZE | none | 0x1 |
_PORTA_CLKO_LENGTH | none | 0x1 |
_PORTA_CLKO_MASK | none | 0x40 |
_PORTA_ULPWUIN_POSN | none | 0x0 |
_PORTA_ULPWUIN_POSITION | none | 0x0 |
_PORTA_ULPWUIN_SIZE | none | 0x1 |
_PORTA_ULPWUIN_LENGTH | none | 0x1 |
_PORTA_ULPWUIN_MASK | none | 0x1 |
PORTB | none | <\077435>PORTB |
PORTB | none | <\077435>PORTB |
_PORTB_RB0_POSN | none | 0x0 |
_PORTB_RB0_POSITION | none | 0x0 |
_PORTB_RB0_SIZE | none | 0x1 |
_PORTB_RB0_LENGTH | none | 0x1 |
_PORTB_RB0_MASK | none | 0x1 |
_PORTB_RB1_POSN | none | 0x1 |
_PORTB_RB1_POSITION | none | 0x1 |
_PORTB_RB1_SIZE | none | 0x1 |
_PORTB_RB1_LENGTH | none | 0x1 |
_PORTB_RB1_MASK | none | 0x2 |
_PORTB_RB2_POSN | none | 0x2 |
_PORTB_RB2_POSITION | none | 0x2 |
_PORTB_RB2_SIZE | none | 0x1 |
_PORTB_RB2_LENGTH | none | 0x1 |
_PORTB_RB2_MASK | none | 0x4 |
_PORTB_RB3_POSN | none | 0x3 |
_PORTB_RB3_POSITION | none | 0x3 |
_PORTB_RB3_SIZE | none | 0x1 |
_PORTB_RB3_LENGTH | none | 0x1 |
_PORTB_RB3_MASK | none | 0x8 |
_PORTB_RB4_POSN | none | 0x4 |
_PORTB_RB4_POSITION | none | 0x4 |
_PORTB_RB4_SIZE | none | 0x1 |
_PORTB_RB4_LENGTH | none | 0x1 |
_PORTB_RB4_MASK | none | 0x10 |
_PORTB_RB5_POSN | none | 0x5 |
_PORTB_RB5_POSITION | none | 0x5 |
_PORTB_RB5_SIZE | none | 0x1 |
_PORTB_RB5_LENGTH | none | 0x1 |
_PORTB_RB5_MASK | none | 0x20 |
_PORTB_RB6_POSN | none | 0x6 |
_PORTB_RB6_POSITION | none | 0x6 |
_PORTB_RB6_SIZE | none | 0x1 |
_PORTB_RB6_LENGTH | none | 0x1 |
_PORTB_RB6_MASK | none | 0x40 |
_PORTB_RB7_POSN | none | 0x7 |
_PORTB_RB7_POSITION | none | 0x7 |
_PORTB_RB7_SIZE | none | 0x1 |
_PORTB_RB7_LENGTH | none | 0x1 |
_PORTB_RB7_MASK | none | 0x80 |
_PORTB_INT0_POSN | none | 0x0 |
_PORTB_INT0_POSITION | none | 0x0 |
_PORTB_INT0_SIZE | none | 0x1 |
_PORTB_INT0_LENGTH | none | 0x1 |
_PORTB_INT0_MASK | none | 0x1 |
_PORTB_INT1_POSN | none | 0x1 |
_PORTB_INT1_POSITION | none | 0x1 |
_PORTB_INT1_SIZE | none | 0x1 |
_PORTB_INT1_LENGTH | none | 0x1 |
_PORTB_INT1_MASK | none | 0x2 |
_PORTB_INT2_POSN | none | 0x2 |
_PORTB_INT2_POSITION | none | 0x2 |
_PORTB_INT2_SIZE | none | 0x1 |
_PORTB_INT2_LENGTH | none | 0x1 |
_PORTB_INT2_MASK | none | 0x4 |
_PORTB_INT3_POSN | none | 0x3 |
_PORTB_INT3_POSITION | none | 0x3 |
_PORTB_INT3_SIZE | none | 0x1 |
_PORTB_INT3_LENGTH | none | 0x1 |
_PORTB_INT3_MASK | none | 0x8 |
_PORTB_KBI0_POSN | none | 0x4 |
_PORTB_KBI0_POSITION | none | 0x4 |
_PORTB_KBI0_SIZE | none | 0x1 |
_PORTB_KBI0_LENGTH | none | 0x1 |
_PORTB_KBI0_MASK | none | 0x10 |
_PORTB_KBI1_POSN | none | 0x5 |
_PORTB_KBI1_POSITION | none | 0x5 |
_PORTB_KBI1_SIZE | none | 0x1 |
_PORTB_KBI1_LENGTH | none | 0x1 |
_PORTB_KBI1_MASK | none | 0x20 |
_PORTB_KBI2_POSN | none | 0x6 |
_PORTB_KBI2_POSITION | none | 0x6 |
_PORTB_KBI2_SIZE | none | 0x1 |
_PORTB_KBI2_LENGTH | none | 0x1 |
_PORTB_KBI2_MASK | none | 0x40 |
_PORTB_KBI3_POSN | none | 0x7 |
_PORTB_KBI3_POSITION | none | 0x7 |
_PORTB_KBI3_SIZE | none | 0x1 |
_PORTB_KBI3_LENGTH | none | 0x1 |
_PORTB_KBI3_MASK | none | 0x80 |
_PORTB_CCP2_POSN | none | 0x3 |
_PORTB_CCP2_POSITION | none | 0x3 |
_PORTB_CCP2_SIZE | none | 0x1 |
_PORTB_CCP2_LENGTH | none | 0x1 |
_PORTB_CCP2_MASK | none | 0x8 |
_PORTB_PGM_POSN | none | 0x5 |
_PORTB_PGM_POSITION | none | 0x5 |
_PORTB_PGM_SIZE | none | 0x1 |
_PORTB_PGM_LENGTH | none | 0x1 |
_PORTB_PGM_MASK | none | 0x20 |
_PORTB_PGC_POSN | none | 0x6 |
_PORTB_PGC_POSITION | none | 0x6 |
_PORTB_PGC_SIZE | none | 0x1 |
_PORTB_PGC_LENGTH | none | 0x1 |
_PORTB_PGC_MASK | none | 0x40 |
_PORTB_PGD_POSN | none | 0x7 |
_PORTB_PGD_POSITION | none | 0x7 |
_PORTB_PGD_SIZE | none | 0x1 |
_PORTB_PGD_LENGTH | none | 0x1 |
_PORTB_PGD_MASK | none | 0x80 |
_PORTB_CCP2A_POSN | none | 0x3 |
_PORTB_CCP2A_POSITION | none | 0x3 |
_PORTB_CCP2A_SIZE | none | 0x1 |
_PORTB_CCP2A_LENGTH | none | 0x1 |
_PORTB_CCP2A_MASK | none | 0x8 |
_PORTB_CCP2_PA2_POSN | none | 0x3 |
_PORTB_CCP2_PA2_POSITION | none | 0x3 |
_PORTB_CCP2_PA2_SIZE | none | 0x1 |
_PORTB_CCP2_PA2_LENGTH | none | 0x1 |
_PORTB_CCP2_PA2_MASK | none | 0x8 |
PORTC | none | <\077435>PORTC |
PORTC | none | <\077435>PORTC |
_PORTC_RC0_POSN | none | 0x0 |
_PORTC_RC0_POSITION | none | 0x0 |
_PORTC_RC0_SIZE | none | 0x1 |
_PORTC_RC0_LENGTH | none | 0x1 |
_PORTC_RC0_MASK | none | 0x1 |
_PORTC_RC1_POSN | none | 0x1 |
_PORTC_RC1_POSITION | none | 0x1 |
_PORTC_RC1_SIZE | none | 0x1 |
_PORTC_RC1_LENGTH | none | 0x1 |
_PORTC_RC1_MASK | none | 0x2 |
_PORTC_RC2_POSN | none | 0x2 |
_PORTC_RC2_POSITION | none | 0x2 |
_PORTC_RC2_SIZE | none | 0x1 |
_PORTC_RC2_LENGTH | none | 0x1 |
_PORTC_RC2_MASK | none | 0x4 |
_PORTC_RC3_POSN | none | 0x3 |
_PORTC_RC3_POSITION | none | 0x3 |
_PORTC_RC3_SIZE | none | 0x1 |
_PORTC_RC3_LENGTH | none | 0x1 |
_PORTC_RC3_MASK | none | 0x8 |
_PORTC_RC4_POSN | none | 0x4 |
_PORTC_RC4_POSITION | none | 0x4 |
_PORTC_RC4_SIZE | none | 0x1 |
_PORTC_RC4_LENGTH | none | 0x1 |
_PORTC_RC4_MASK | none | 0x10 |
_PORTC_RC5_POSN | none | 0x5 |
_PORTC_RC5_POSITION | none | 0x5 |
_PORTC_RC5_SIZE | none | 0x1 |
_PORTC_RC5_LENGTH | none | 0x1 |
_PORTC_RC5_MASK | none | 0x20 |
_PORTC_RC6_POSN | none | 0x6 |
_PORTC_RC6_POSITION | none | 0x6 |
_PORTC_RC6_SIZE | none | 0x1 |
_PORTC_RC6_LENGTH | none | 0x1 |
_PORTC_RC6_MASK | none | 0x40 |
_PORTC_RC7_POSN | none | 0x7 |
_PORTC_RC7_POSITION | none | 0x7 |
_PORTC_RC7_SIZE | none | 0x1 |
_PORTC_RC7_LENGTH | none | 0x1 |
_PORTC_RC7_MASK | none | 0x80 |
_PORTC_T1OSO_POSN | none | 0x0 |
_PORTC_T1OSO_POSITION | none | 0x0 |
_PORTC_T1OSO_SIZE | none | 0x1 |
_PORTC_T1OSO_LENGTH | none | 0x1 |
_PORTC_T1OSO_MASK | none | 0x1 |
_PORTC_T1OSI_POSN | none | 0x1 |
_PORTC_T1OSI_POSITION | none | 0x1 |
_PORTC_T1OSI_SIZE | none | 0x1 |
_PORTC_T1OSI_LENGTH | none | 0x1 |
_PORTC_T1OSI_MASK | none | 0x2 |
_PORTC_CCP1_POSN | none | 0x2 |
_PORTC_CCP1_POSITION | none | 0x2 |
_PORTC_CCP1_SIZE | none | 0x1 |
_PORTC_CCP1_LENGTH | none | 0x1 |
_PORTC_CCP1_MASK | none | 0x4 |
_PORTC_SCK_POSN | none | 0x3 |
_PORTC_SCK_POSITION | none | 0x3 |
_PORTC_SCK_SIZE | none | 0x1 |
_PORTC_SCK_LENGTH | none | 0x1 |
_PORTC_SCK_MASK | none | 0x8 |
_PORTC_SDI_POSN | none | 0x4 |
_PORTC_SDI_POSITION | none | 0x4 |
_PORTC_SDI_SIZE | none | 0x1 |
_PORTC_SDI_LENGTH | none | 0x1 |
_PORTC_SDI_MASK | none | 0x10 |
_PORTC_SDO_POSN | none | 0x5 |
_PORTC_SDO_POSITION | none | 0x5 |
_PORTC_SDO_SIZE | none | 0x1 |
_PORTC_SDO_LENGTH | none | 0x1 |
_PORTC_SDO_MASK | none | 0x20 |
_PORTC_TX_POSN | none | 0x6 |
_PORTC_TX_POSITION | none | 0x6 |
_PORTC_TX_SIZE | none | 0x1 |
_PORTC_TX_LENGTH | none | 0x1 |
_PORTC_TX_MASK | none | 0x40 |
_PORTC_RX_POSN | none | 0x7 |
_PORTC_RX_POSITION | none | 0x7 |
_PORTC_RX_SIZE | none | 0x1 |
_PORTC_RX_LENGTH | none | 0x1 |
_PORTC_RX_MASK | none | 0x80 |
_PORTC_T13CKI_POSN | none | 0x0 |
_PORTC_T13CKI_POSITION | none | 0x0 |
_PORTC_T13CKI_SIZE | none | 0x1 |
_PORTC_T13CKI_LENGTH | none | 0x1 |
_PORTC_T13CKI_MASK | none | 0x1 |
_PORTC_CCP2_POSN | none | 0x1 |
_PORTC_CCP2_POSITION | none | 0x1 |
_PORTC_CCP2_SIZE | none | 0x1 |
_PORTC_CCP2_LENGTH | none | 0x1 |
_PORTC_CCP2_MASK | none | 0x2 |
_PORTC_SCL_POSN | none | 0x3 |
_PORTC_SCL_POSITION | none | 0x3 |
_PORTC_SCL_SIZE | none | 0x1 |
_PORTC_SCL_LENGTH | none | 0x1 |
_PORTC_SCL_MASK | none | 0x8 |
_PORTC_SDA_POSN | none | 0x4 |
_PORTC_SDA_POSITION | none | 0x4 |
_PORTC_SDA_SIZE | none | 0x1 |
_PORTC_SDA_LENGTH | none | 0x1 |
_PORTC_SDA_MASK | none | 0x10 |
_PORTC_CK_POSN | none | 0x6 |
_PORTC_CK_POSITION | none | 0x6 |
_PORTC_CK_SIZE | none | 0x1 |
_PORTC_CK_LENGTH | none | 0x1 |
_PORTC_CK_MASK | none | 0x40 |
_PORTC_DT_POSN | none | 0x7 |
_PORTC_DT_POSITION | none | 0x7 |
_PORTC_DT_SIZE | none | 0x1 |
_PORTC_DT_LENGTH | none | 0x1 |
_PORTC_DT_MASK | none | 0x80 |
_PORTC_CCP2A_POSN | none | 0x1 |
_PORTC_CCP2A_POSITION | none | 0x1 |
_PORTC_CCP2A_SIZE | none | 0x1 |
_PORTC_CCP2A_LENGTH | none | 0x1 |
_PORTC_CCP2A_MASK | none | 0x2 |
_PORTC_PA2_POSN | none | 0x1 |
_PORTC_PA2_POSITION | none | 0x1 |
_PORTC_PA2_SIZE | none | 0x1 |
_PORTC_PA2_LENGTH | none | 0x1 |
_PORTC_PA2_MASK | none | 0x2 |
_PORTC_PA1_POSN | none | 0x2 |
_PORTC_PA1_POSITION | none | 0x2 |
_PORTC_PA1_SIZE | none | 0x1 |
_PORTC_PA1_LENGTH | none | 0x1 |
_PORTC_PA1_MASK | none | 0x4 |
PORTD | none | <\077435>PORTD |
PORTD | none | <\077435>PORTD |
_PORTD_RD0_POSN | none | 0x0 |
_PORTD_RD0_POSITION | none | 0x0 |
_PORTD_RD0_SIZE | none | 0x1 |
_PORTD_RD0_LENGTH | none | 0x1 |
_PORTD_RD0_MASK | none | 0x1 |
_PORTD_RD1_POSN | none | 0x1 |
_PORTD_RD1_POSITION | none | 0x1 |
_PORTD_RD1_SIZE | none | 0x1 |
_PORTD_RD1_LENGTH | none | 0x1 |
_PORTD_RD1_MASK | none | 0x2 |
_PORTD_RD2_POSN | none | 0x2 |
_PORTD_RD2_POSITION | none | 0x2 |
_PORTD_RD2_SIZE | none | 0x1 |
_PORTD_RD2_LENGTH | none | 0x1 |
_PORTD_RD2_MASK | none | 0x4 |
_PORTD_RD3_POSN | none | 0x3 |
_PORTD_RD3_POSITION | none | 0x3 |
_PORTD_RD3_SIZE | none | 0x1 |
_PORTD_RD3_LENGTH | none | 0x1 |
_PORTD_RD3_MASK | none | 0x8 |
_PORTD_RD4_POSN | none | 0x4 |
_PORTD_RD4_POSITION | none | 0x4 |
_PORTD_RD4_SIZE | none | 0x1 |
_PORTD_RD4_LENGTH | none | 0x1 |
_PORTD_RD4_MASK | none | 0x10 |
_PORTD_RD5_POSN | none | 0x5 |
_PORTD_RD5_POSITION | none | 0x5 |
_PORTD_RD5_SIZE | none | 0x1 |
_PORTD_RD5_LENGTH | none | 0x1 |
_PORTD_RD5_MASK | none | 0x20 |
_PORTD_RD6_POSN | none | 0x6 |
_PORTD_RD6_POSITION | none | 0x6 |
_PORTD_RD6_SIZE | none | 0x1 |
_PORTD_RD6_LENGTH | none | 0x1 |
_PORTD_RD6_MASK | none | 0x40 |
_PORTD_RD7_POSN | none | 0x7 |
_PORTD_RD7_POSITION | none | 0x7 |
_PORTD_RD7_SIZE | none | 0x1 |
_PORTD_RD7_LENGTH | none | 0x1 |
_PORTD_RD7_MASK | none | 0x80 |
_PORTD_PSP0_POSN | none | 0x0 |
_PORTD_PSP0_POSITION | none | 0x0 |
_PORTD_PSP0_SIZE | none | 0x1 |
_PORTD_PSP0_LENGTH | none | 0x1 |
_PORTD_PSP0_MASK | none | 0x1 |
_PORTD_PSP1_POSN | none | 0x1 |
_PORTD_PSP1_POSITION | none | 0x1 |
_PORTD_PSP1_SIZE | none | 0x1 |
_PORTD_PSP1_LENGTH | none | 0x1 |
_PORTD_PSP1_MASK | none | 0x2 |
_PORTD_PSP2_POSN | none | 0x2 |
_PORTD_PSP2_POSITION | none | 0x2 |
_PORTD_PSP2_SIZE | none | 0x1 |
_PORTD_PSP2_LENGTH | none | 0x1 |
_PORTD_PSP2_MASK | none | 0x4 |
_PORTD_PSP3_POSN | none | 0x3 |
_PORTD_PSP3_POSITION | none | 0x3 |
_PORTD_PSP3_SIZE | none | 0x1 |
_PORTD_PSP3_LENGTH | none | 0x1 |
_PORTD_PSP3_MASK | none | 0x8 |
_PORTD_PSP4_POSN | none | 0x4 |
_PORTD_PSP4_POSITION | none | 0x4 |
_PORTD_PSP4_SIZE | none | 0x1 |
_PORTD_PSP4_LENGTH | none | 0x1 |
_PORTD_PSP4_MASK | none | 0x10 |
_PORTD_PSP5_POSN | none | 0x5 |
_PORTD_PSP5_POSITION | none | 0x5 |
_PORTD_PSP5_SIZE | none | 0x1 |
_PORTD_PSP5_LENGTH | none | 0x1 |
_PORTD_PSP5_MASK | none | 0x20 |
_PORTD_PSP6_POSN | none | 0x6 |
_PORTD_PSP6_POSITION | none | 0x6 |
_PORTD_PSP6_SIZE | none | 0x1 |
_PORTD_PSP6_LENGTH | none | 0x1 |
_PORTD_PSP6_MASK | none | 0x40 |
_PORTD_PSP7_POSN | none | 0x7 |
_PORTD_PSP7_POSITION | none | 0x7 |
_PORTD_PSP7_SIZE | none | 0x1 |
_PORTD_PSP7_LENGTH | none | 0x1 |
_PORTD_PSP7_MASK | none | 0x80 |
_PORTD_AD0_POSN | none | 0x0 |
_PORTD_AD0_POSITION | none | 0x0 |
_PORTD_AD0_SIZE | none | 0x1 |
_PORTD_AD0_LENGTH | none | 0x1 |
_PORTD_AD0_MASK | none | 0x1 |
_PORTD_AD1_POSN | none | 0x1 |
_PORTD_AD1_POSITION | none | 0x1 |
_PORTD_AD1_SIZE | none | 0x1 |
_PORTD_AD1_LENGTH | none | 0x1 |
_PORTD_AD1_MASK | none | 0x2 |
_PORTD_AD2_POSN | none | 0x2 |
_PORTD_AD2_POSITION | none | 0x2 |
_PORTD_AD2_SIZE | none | 0x1 |
_PORTD_AD2_LENGTH | none | 0x1 |
_PORTD_AD2_MASK | none | 0x4 |
_PORTD_AD3_POSN | none | 0x3 |
_PORTD_AD3_POSITION | none | 0x3 |
_PORTD_AD3_SIZE | none | 0x1 |
_PORTD_AD3_LENGTH | none | 0x1 |
_PORTD_AD3_MASK | none | 0x8 |
_PORTD_AD4_POSN | none | 0x4 |
_PORTD_AD4_POSITION | none | 0x4 |
_PORTD_AD4_SIZE | none | 0x1 |
_PORTD_AD4_LENGTH | none | 0x1 |
_PORTD_AD4_MASK | none | 0x10 |
_PORTD_AD5_POSN | none | 0x5 |
_PORTD_AD5_POSITION | none | 0x5 |
_PORTD_AD5_SIZE | none | 0x1 |
_PORTD_AD5_LENGTH | none | 0x1 |
_PORTD_AD5_MASK | none | 0x20 |
_PORTD_AD6_POSN | none | 0x6 |
_PORTD_AD6_POSITION | none | 0x6 |
_PORTD_AD6_SIZE | none | 0x1 |
_PORTD_AD6_LENGTH | none | 0x1 |
_PORTD_AD6_MASK | none | 0x40 |
_PORTD_AD7_POSN | none | 0x7 |
_PORTD_AD7_POSITION | none | 0x7 |
_PORTD_AD7_SIZE | none | 0x1 |
_PORTD_AD7_LENGTH | none | 0x1 |
_PORTD_AD7_MASK | none | 0x80 |
_PORTD_AD00_POSN | none | 0x0 |
_PORTD_AD00_POSITION | none | 0x0 |
_PORTD_AD00_SIZE | none | 0x1 |
_PORTD_AD00_LENGTH | none | 0x1 |
_PORTD_AD00_MASK | none | 0x1 |
_PORTD_AD01_POSN | none | 0x1 |
_PORTD_AD01_POSITION | none | 0x1 |
_PORTD_AD01_SIZE | none | 0x1 |
_PORTD_AD01_LENGTH | none | 0x1 |
_PORTD_AD01_MASK | none | 0x2 |
_PORTD_AD02_POSN | none | 0x2 |
_PORTD_AD02_POSITION | none | 0x2 |
_PORTD_AD02_SIZE | none | 0x1 |
_PORTD_AD02_LENGTH | none | 0x1 |
_PORTD_AD02_MASK | none | 0x4 |
_PORTD_AD03_POSN | none | 0x3 |
_PORTD_AD03_POSITION | none | 0x3 |
_PORTD_AD03_SIZE | none | 0x1 |
_PORTD_AD03_LENGTH | none | 0x1 |
_PORTD_AD03_MASK | none | 0x8 |
_PORTD_AD04_POSN | none | 0x4 |
_PORTD_AD04_POSITION | none | 0x4 |
_PORTD_AD04_SIZE | none | 0x1 |
_PORTD_AD04_LENGTH | none | 0x1 |
_PORTD_AD04_MASK | none | 0x10 |
_PORTD_AD05_POSN | none | 0x5 |
_PORTD_AD05_POSITION | none | 0x5 |
_PORTD_AD05_SIZE | none | 0x1 |
_PORTD_AD05_LENGTH | none | 0x1 |
_PORTD_AD05_MASK | none | 0x20 |
_PORTD_AD06_POSN | none | 0x6 |
_PORTD_AD06_POSITION | none | 0x6 |
_PORTD_AD06_SIZE | none | 0x1 |
_PORTD_AD06_LENGTH | none | 0x1 |
_PORTD_AD06_MASK | none | 0x40 |
_PORTD_AD07_POSN | none | 0x7 |
_PORTD_AD07_POSITION | none | 0x7 |
_PORTD_AD07_SIZE | none | 0x1 |
_PORTD_AD07_LENGTH | none | 0x1 |
_PORTD_AD07_MASK | none | 0x80 |
_PORTD_SS2_POSN | none | 0x7 |
_PORTD_SS2_POSITION | none | 0x7 |
_PORTD_SS2_SIZE | none | 0x1 |
_PORTD_SS2_LENGTH | none | 0x1 |
_PORTD_SS2_MASK | none | 0x80 |
PORTE | none | <\077435>PORTE |
PORTE | none | <\077435>PORTE |
_PORTE_RE0_POSN | none | 0x0 |
_PORTE_RE0_POSITION | none | 0x0 |
_PORTE_RE0_SIZE | none | 0x1 |
_PORTE_RE0_LENGTH | none | 0x1 |
_PORTE_RE0_MASK | none | 0x1 |
_PORTE_RE1_POSN | none | 0x1 |
_PORTE_RE1_POSITION | none | 0x1 |
_PORTE_RE1_SIZE | none | 0x1 |
_PORTE_RE1_LENGTH | none | 0x1 |
_PORTE_RE1_MASK | none | 0x2 |
_PORTE_RE2_POSN | none | 0x2 |
_PORTE_RE2_POSITION | none | 0x2 |
_PORTE_RE2_SIZE | none | 0x1 |
_PORTE_RE2_LENGTH | none | 0x1 |
_PORTE_RE2_MASK | none | 0x4 |
_PORTE_RE3_POSN | none | 0x3 |
_PORTE_RE3_POSITION | none | 0x3 |
_PORTE_RE3_SIZE | none | 0x1 |
_PORTE_RE3_LENGTH | none | 0x1 |
_PORTE_RE3_MASK | none | 0x8 |
_PORTE_RE4_POSN | none | 0x4 |
_PORTE_RE4_POSITION | none | 0x4 |
_PORTE_RE4_SIZE | none | 0x1 |
_PORTE_RE4_LENGTH | none | 0x1 |
_PORTE_RE4_MASK | none | 0x10 |
_PORTE_RE5_POSN | none | 0x5 |
_PORTE_RE5_POSITION | none | 0x5 |
_PORTE_RE5_SIZE | none | 0x1 |
_PORTE_RE5_LENGTH | none | 0x1 |
_PORTE_RE5_MASK | none | 0x20 |
_PORTE_RE6_POSN | none | 0x6 |
_PORTE_RE6_POSITION | none | 0x6 |
_PORTE_RE6_SIZE | none | 0x1 |
_PORTE_RE6_LENGTH | none | 0x1 |
_PORTE_RE6_MASK | none | 0x40 |
_PORTE_RE7_POSN | none | 0x7 |
_PORTE_RE7_POSITION | none | 0x7 |
_PORTE_RE7_SIZE | none | 0x1 |
_PORTE_RE7_LENGTH | none | 0x1 |
_PORTE_RE7_MASK | none | 0x80 |
_PORTE_RD_POSN | none | 0x0 |
_PORTE_RD_POSITION | none | 0x0 |
_PORTE_RD_SIZE | none | 0x1 |
_PORTE_RD_LENGTH | none | 0x1 |
_PORTE_RD_MASK | none | 0x1 |
_PORTE_WR_POSN | none | 0x1 |
_PORTE_WR_POSITION | none | 0x1 |
_PORTE_WR_SIZE | none | 0x1 |
_PORTE_WR_LENGTH | none | 0x1 |
_PORTE_WR_MASK | none | 0x2 |
_PORTE_CS_POSN | none | 0x2 |
_PORTE_CS_POSITION | none | 0x2 |
_PORTE_CS_SIZE | none | 0x1 |
_PORTE_CS_LENGTH | none | 0x1 |
_PORTE_CS_MASK | none | 0x4 |
_PORTE_CCP2_POSN | none | 0x7 |
_PORTE_CCP2_POSITION | none | 0x7 |
_PORTE_CCP2_SIZE | none | 0x1 |
_PORTE_CCP2_LENGTH | none | 0x1 |
_PORTE_CCP2_MASK | none | 0x80 |
_PORTE_AD8_POSN | none | 0x0 |
_PORTE_AD8_POSITION | none | 0x0 |
_PORTE_AD8_SIZE | none | 0x1 |
_PORTE_AD8_LENGTH | none | 0x1 |
_PORTE_AD8_MASK | none | 0x1 |
_PORTE_AD9_POSN | none | 0x1 |
_PORTE_AD9_POSITION | none | 0x1 |
_PORTE_AD9_SIZE | none | 0x1 |
_PORTE_AD9_LENGTH | none | 0x1 |
_PORTE_AD9_MASK | none | 0x2 |
_PORTE_AD10_POSN | none | 0x2 |
_PORTE_AD10_POSITION | none | 0x2 |
_PORTE_AD10_SIZE | none | 0x1 |
_PORTE_AD10_LENGTH | none | 0x1 |
_PORTE_AD10_MASK | none | 0x4 |
_PORTE_AD11_POSN | none | 0x3 |
_PORTE_AD11_POSITION | none | 0x3 |
_PORTE_AD11_SIZE | none | 0x1 |
_PORTE_AD11_LENGTH | none | 0x1 |
_PORTE_AD11_MASK | none | 0x8 |
_PORTE_AD12_POSN | none | 0x4 |
_PORTE_AD12_POSITION | none | 0x4 |
_PORTE_AD12_SIZE | none | 0x1 |
_PORTE_AD12_LENGTH | none | 0x1 |
_PORTE_AD12_MASK | none | 0x10 |
_PORTE_AD13_POSN | none | 0x5 |
_PORTE_AD13_POSITION | none | 0x5 |
_PORTE_AD13_SIZE | none | 0x1 |
_PORTE_AD13_LENGTH | none | 0x1 |
_PORTE_AD13_MASK | none | 0x20 |
_PORTE_AD14_POSN | none | 0x6 |
_PORTE_AD14_POSITION | none | 0x6 |
_PORTE_AD14_SIZE | none | 0x1 |
_PORTE_AD14_LENGTH | none | 0x1 |
_PORTE_AD14_MASK | none | 0x40 |
_PORTE_AD15_POSN | none | 0x7 |
_PORTE_AD15_POSITION | none | 0x7 |
_PORTE_AD15_SIZE | none | 0x1 |
_PORTE_AD15_LENGTH | none | 0x1 |
_PORTE_AD15_MASK | none | 0x80 |
_PORTE_AD08_POSN | none | 0x0 |
_PORTE_AD08_POSITION | none | 0x0 |
_PORTE_AD08_SIZE | none | 0x1 |
_PORTE_AD08_LENGTH | none | 0x1 |
_PORTE_AD08_MASK | none | 0x1 |
_PORTE_AD09_POSN | none | 0x1 |
_PORTE_AD09_POSITION | none | 0x1 |
_PORTE_AD09_SIZE | none | 0x1 |
_PORTE_AD09_LENGTH | none | 0x1 |
_PORTE_AD09_MASK | none | 0x2 |
_PORTE_CCP2C_POSN | none | 0x7 |
_PORTE_CCP2C_POSITION | none | 0x7 |
_PORTE_CCP2C_SIZE | none | 0x1 |
_PORTE_CCP2C_LENGTH | none | 0x1 |
_PORTE_CCP2C_MASK | none | 0x80 |
_PORTE_PD2_POSN | none | 0x0 |
_PORTE_PD2_POSITION | none | 0x0 |
_PORTE_PD2_SIZE | none | 0x1 |
_PORTE_PD2_LENGTH | none | 0x1 |
_PORTE_PD2_MASK | none | 0x1 |
_PORTE_PC2_POSN | none | 0x1 |
_PORTE_PC2_POSITION | none | 0x1 |
_PORTE_PC2_SIZE | none | 0x1 |
_PORTE_PC2_LENGTH | none | 0x1 |
_PORTE_PC2_MASK | none | 0x2 |
_PORTE_CCP10_POSN | none | 0x2 |
_PORTE_CCP10_POSITION | none | 0x2 |
_PORTE_CCP10_SIZE | none | 0x1 |
_PORTE_CCP10_LENGTH | none | 0x1 |
_PORTE_CCP10_MASK | none | 0x4 |
_PORTE_CCP9E_POSN | none | 0x3 |
_PORTE_CCP9E_POSITION | none | 0x3 |
_PORTE_CCP9E_SIZE | none | 0x1 |
_PORTE_CCP9E_LENGTH | none | 0x1 |
_PORTE_CCP9E_MASK | none | 0x8 |
_PORTE_CCP8E_POSN | none | 0x4 |
_PORTE_CCP8E_POSITION | none | 0x4 |
_PORTE_CCP8E_SIZE | none | 0x1 |
_PORTE_CCP8E_LENGTH | none | 0x1 |
_PORTE_CCP8E_MASK | none | 0x10 |
_PORTE_CCP7E_POSN | none | 0x5 |
_PORTE_CCP7E_POSITION | none | 0x5 |
_PORTE_CCP7E_SIZE | none | 0x1 |
_PORTE_CCP7E_LENGTH | none | 0x1 |
_PORTE_CCP7E_MASK | none | 0x20 |
_PORTE_CCP6E_POSN | none | 0x6 |
_PORTE_CCP6E_POSITION | none | 0x6 |
_PORTE_CCP6E_SIZE | none | 0x1 |
_PORTE_CCP6E_LENGTH | none | 0x1 |
_PORTE_CCP6E_MASK | none | 0x40 |
_PORTE_CCP2E_POSN | none | 0x7 |
_PORTE_CCP2E_POSITION | none | 0x7 |
_PORTE_CCP2E_SIZE | none | 0x1 |
_PORTE_CCP2E_LENGTH | none | 0x1 |
_PORTE_CCP2E_MASK | none | 0x80 |
_PORTE_RDE_POSN | none | 0x0 |
_PORTE_RDE_POSITION | none | 0x0 |
_PORTE_RDE_SIZE | none | 0x1 |
_PORTE_RDE_LENGTH | none | 0x1 |
_PORTE_RDE_MASK | none | 0x1 |
_PORTE_WRE_POSN | none | 0x1 |
_PORTE_WRE_POSITION | none | 0x1 |
_PORTE_WRE_SIZE | none | 0x1 |
_PORTE_WRE_LENGTH | none | 0x1 |
_PORTE_WRE_MASK | none | 0x2 |
_PORTE_PB2_POSN | none | 0x2 |
_PORTE_PB2_POSITION | none | 0x2 |
_PORTE_PB2_SIZE | none | 0x1 |
_PORTE_PB2_LENGTH | none | 0x1 |
_PORTE_PB2_MASK | none | 0x4 |
_PORTE_PC3E_POSN | none | 0x3 |
_PORTE_PC3E_POSITION | none | 0x3 |
_PORTE_PC3E_SIZE | none | 0x1 |
_PORTE_PC3E_LENGTH | none | 0x1 |
_PORTE_PC3E_MASK | none | 0x8 |
_PORTE_PB3E_POSN | none | 0x4 |
_PORTE_PB3E_POSITION | none | 0x4 |
_PORTE_PB3E_SIZE | none | 0x1 |
_PORTE_PB3E_LENGTH | none | 0x1 |
_PORTE_PB3E_MASK | none | 0x10 |
_PORTE_PC1E_POSN | none | 0x5 |
_PORTE_PC1E_POSITION | none | 0x5 |
_PORTE_PC1E_SIZE | none | 0x1 |
_PORTE_PC1E_LENGTH | none | 0x1 |
_PORTE_PC1E_MASK | none | 0x20 |
_PORTE_PB1E_POSN | none | 0x6 |
_PORTE_PB1E_POSITION | none | 0x6 |
_PORTE_PB1E_SIZE | none | 0x1 |
_PORTE_PB1E_LENGTH | none | 0x1 |
_PORTE_PB1E_MASK | none | 0x40 |
_PORTE_PA2E_POSN | none | 0x7 |
_PORTE_PA2E_POSITION | none | 0x7 |
_PORTE_PA2E_SIZE | none | 0x1 |
_PORTE_PA2E_LENGTH | none | 0x1 |
_PORTE_PA2E_MASK | none | 0x80 |
PORTF | none | <\077435>PORTF |
PORTF | none | <\077435>PORTF |
_PORTF_RF0_POSN | none | 0x0 |
_PORTF_RF0_POSITION | none | 0x0 |
_PORTF_RF0_SIZE | none | 0x1 |
_PORTF_RF0_LENGTH | none | 0x1 |
_PORTF_RF0_MASK | none | 0x1 |
_PORTF_RF1_POSN | none | 0x1 |
_PORTF_RF1_POSITION | none | 0x1 |
_PORTF_RF1_SIZE | none | 0x1 |
_PORTF_RF1_LENGTH | none | 0x1 |
_PORTF_RF1_MASK | none | 0x2 |
_PORTF_RF2_POSN | none | 0x2 |
_PORTF_RF2_POSITION | none | 0x2 |
_PORTF_RF2_SIZE | none | 0x1 |
_PORTF_RF2_LENGTH | none | 0x1 |
_PORTF_RF2_MASK | none | 0x4 |
_PORTF_RF3_POSN | none | 0x3 |
_PORTF_RF3_POSITION | none | 0x3 |
_PORTF_RF3_SIZE | none | 0x1 |
_PORTF_RF3_LENGTH | none | 0x1 |
_PORTF_RF3_MASK | none | 0x8 |
_PORTF_RF4_POSN | none | 0x4 |
_PORTF_RF4_POSITION | none | 0x4 |
_PORTF_RF4_SIZE | none | 0x1 |
_PORTF_RF4_LENGTH | none | 0x1 |
_PORTF_RF4_MASK | none | 0x10 |
_PORTF_RF5_POSN | none | 0x5 |
_PORTF_RF5_POSITION | none | 0x5 |
_PORTF_RF5_SIZE | none | 0x1 |
_PORTF_RF5_LENGTH | none | 0x1 |
_PORTF_RF5_MASK | none | 0x20 |
_PORTF_RF6_POSN | none | 0x6 |
_PORTF_RF6_POSITION | none | 0x6 |
_PORTF_RF6_SIZE | none | 0x1 |
_PORTF_RF6_LENGTH | none | 0x1 |
_PORTF_RF6_MASK | none | 0x40 |
_PORTF_RF7_POSN | none | 0x7 |
_PORTF_RF7_POSITION | none | 0x7 |
_PORTF_RF7_SIZE | none | 0x1 |
_PORTF_RF7_LENGTH | none | 0x1 |
_PORTF_RF7_MASK | none | 0x80 |
_PORTF_AN5_POSN | none | 0x0 |
_PORTF_AN5_POSITION | none | 0x0 |
_PORTF_AN5_SIZE | none | 0x1 |
_PORTF_AN5_LENGTH | none | 0x1 |
_PORTF_AN5_MASK | none | 0x1 |
_PORTF_AN6_POSN | none | 0x1 |
_PORTF_AN6_POSITION | none | 0x1 |
_PORTF_AN6_SIZE | none | 0x1 |
_PORTF_AN6_LENGTH | none | 0x1 |
_PORTF_AN6_MASK | none | 0x2 |
_PORTF_AN7_POSN | none | 0x2 |
_PORTF_AN7_POSITION | none | 0x2 |
_PORTF_AN7_SIZE | none | 0x1 |
_PORTF_AN7_LENGTH | none | 0x1 |
_PORTF_AN7_MASK | none | 0x4 |
_PORTF_AN8_POSN | none | 0x3 |
_PORTF_AN8_POSITION | none | 0x3 |
_PORTF_AN8_SIZE | none | 0x1 |
_PORTF_AN8_LENGTH | none | 0x1 |
_PORTF_AN8_MASK | none | 0x8 |
_PORTF_AN9_POSN | none | 0x4 |
_PORTF_AN9_POSITION | none | 0x4 |
_PORTF_AN9_SIZE | none | 0x1 |
_PORTF_AN9_LENGTH | none | 0x1 |
_PORTF_AN9_MASK | none | 0x10 |
_PORTF_AN10_POSN | none | 0x5 |
_PORTF_AN10_POSITION | none | 0x5 |
_PORTF_AN10_SIZE | none | 0x1 |
_PORTF_AN10_LENGTH | none | 0x1 |
_PORTF_AN10_MASK | none | 0x20 |
_PORTF_AN11_POSN | none | 0x6 |
_PORTF_AN11_POSITION | none | 0x6 |
_PORTF_AN11_SIZE | none | 0x1 |
_PORTF_AN11_LENGTH | none | 0x1 |
_PORTF_AN11_MASK | none | 0x40 |
_PORTF_SS_POSN | none | 0x7 |
_PORTF_SS_POSITION | none | 0x7 |
_PORTF_SS_SIZE | none | 0x1 |
_PORTF_SS_LENGTH | none | 0x1 |
_PORTF_SS_MASK | none | 0x80 |
_PORTF_C2OUT_POSN | none | 0x1 |
_PORTF_C2OUT_POSITION | none | 0x1 |
_PORTF_C2OUT_SIZE | none | 0x1 |
_PORTF_C2OUT_LENGTH | none | 0x1 |
_PORTF_C2OUT_MASK | none | 0x2 |
_PORTF_C1OUT_POSN | none | 0x2 |
_PORTF_C1OUT_POSITION | none | 0x2 |
_PORTF_C1OUT_SIZE | none | 0x1 |
_PORTF_C1OUT_LENGTH | none | 0x1 |
_PORTF_C1OUT_MASK | none | 0x4 |
_PORTF_CVREF_POSN | none | 0x5 |
_PORTF_CVREF_POSITION | none | 0x5 |
_PORTF_CVREF_SIZE | none | 0x1 |
_PORTF_CVREF_LENGTH | none | 0x1 |
_PORTF_CVREF_MASK | none | 0x20 |
_PORTF_C2OUTF_POSN | none | 0x1 |
_PORTF_C2OUTF_POSITION | none | 0x1 |
_PORTF_C2OUTF_SIZE | none | 0x1 |
_PORTF_C2OUTF_LENGTH | none | 0x1 |
_PORTF_C2OUTF_MASK | none | 0x2 |
_PORTF_C1OUTF_POSN | none | 0x2 |
_PORTF_C1OUTF_POSITION | none | 0x2 |
_PORTF_C1OUTF_SIZE | none | 0x1 |
_PORTF_C1OUTF_LENGTH | none | 0x1 |
_PORTF_C1OUTF_MASK | none | 0x4 |
PORTG | none | <\077435>PORTG |
PORTG | none | <\077435>PORTG |
_PORTG_RG0_POSN | none | 0x0 |
_PORTG_RG0_POSITION | none | 0x0 |
_PORTG_RG0_SIZE | none | 0x1 |
_PORTG_RG0_LENGTH | none | 0x1 |
_PORTG_RG0_MASK | none | 0x1 |
_PORTG_RG1_POSN | none | 0x1 |
_PORTG_RG1_POSITION | none | 0x1 |
_PORTG_RG1_SIZE | none | 0x1 |
_PORTG_RG1_LENGTH | none | 0x1 |
_PORTG_RG1_MASK | none | 0x2 |
_PORTG_RG2_POSN | none | 0x2 |
_PORTG_RG2_POSITION | none | 0x2 |
_PORTG_RG2_SIZE | none | 0x1 |
_PORTG_RG2_LENGTH | none | 0x1 |
_PORTG_RG2_MASK | none | 0x4 |
_PORTG_RG3_POSN | none | 0x3 |
_PORTG_RG3_POSITION | none | 0x3 |
_PORTG_RG3_SIZE | none | 0x1 |
_PORTG_RG3_LENGTH | none | 0x1 |
_PORTG_RG3_MASK | none | 0x8 |
_PORTG_RG4_POSN | none | 0x4 |
_PORTG_RG4_POSITION | none | 0x4 |
_PORTG_RG4_SIZE | none | 0x1 |
_PORTG_RG4_LENGTH | none | 0x1 |
_PORTG_RG4_MASK | none | 0x10 |
_PORTG_CCP3_POSN | none | 0x0 |
_PORTG_CCP3_POSITION | none | 0x0 |
_PORTG_CCP3_SIZE | none | 0x1 |
_PORTG_CCP3_LENGTH | none | 0x1 |
_PORTG_CCP3_MASK | none | 0x1 |
_PORTG_TX2_POSN | none | 0x1 |
_PORTG_TX2_POSITION | none | 0x1 |
_PORTG_TX2_SIZE | none | 0x1 |
_PORTG_TX2_LENGTH | none | 0x1 |
_PORTG_TX2_MASK | none | 0x2 |
_PORTG_RX2_POSN | none | 0x2 |
_PORTG_RX2_POSITION | none | 0x2 |
_PORTG_RX2_SIZE | none | 0x1 |
_PORTG_RX2_LENGTH | none | 0x1 |
_PORTG_RX2_MASK | none | 0x4 |
_PORTG_CCP4_POSN | none | 0x3 |
_PORTG_CCP4_POSITION | none | 0x3 |
_PORTG_CCP4_SIZE | none | 0x1 |
_PORTG_CCP4_LENGTH | none | 0x1 |
_PORTG_CCP4_MASK | none | 0x8 |
_PORTG_CCP5_POSN | none | 0x4 |
_PORTG_CCP5_POSITION | none | 0x4 |
_PORTG_CCP5_SIZE | none | 0x1 |
_PORTG_CCP5_LENGTH | none | 0x1 |
_PORTG_CCP5_MASK | none | 0x10 |
_PORTG_CK2_POSN | none | 0x1 |
_PORTG_CK2_POSITION | none | 0x1 |
_PORTG_CK2_SIZE | none | 0x1 |
_PORTG_CK2_LENGTH | none | 0x1 |
_PORTG_CK2_MASK | none | 0x2 |
_PORTG_DT2_POSN | none | 0x2 |
_PORTG_DT2_POSITION | none | 0x2 |
_PORTG_DT2_SIZE | none | 0x1 |
_PORTG_DT2_LENGTH | none | 0x1 |
_PORTG_DT2_MASK | none | 0x4 |
_PORTG_C3OUTG_POSN | none | 0x1 |
_PORTG_C3OUTG_POSITION | none | 0x1 |
_PORTG_C3OUTG_SIZE | none | 0x1 |
_PORTG_C3OUTG_LENGTH | none | 0x1 |
_PORTG_C3OUTG_MASK | none | 0x2 |
PORTH | none | <\077435>PORTH |
PORTH | none | <\077435>PORTH |
_PORTH_RH0_POSN | none | 0x0 |
_PORTH_RH0_POSITION | none | 0x0 |
_PORTH_RH0_SIZE | none | 0x1 |
_PORTH_RH0_LENGTH | none | 0x1 |
_PORTH_RH0_MASK | none | 0x1 |
_PORTH_RH1_POSN | none | 0x1 |
_PORTH_RH1_POSITION | none | 0x1 |
_PORTH_RH1_SIZE | none | 0x1 |
_PORTH_RH1_LENGTH | none | 0x1 |
_PORTH_RH1_MASK | none | 0x2 |
_PORTH_RH2_POSN | none | 0x2 |
_PORTH_RH2_POSITION | none | 0x2 |
_PORTH_RH2_SIZE | none | 0x1 |
_PORTH_RH2_LENGTH | none | 0x1 |
_PORTH_RH2_MASK | none | 0x4 |
_PORTH_RH3_POSN | none | 0x3 |
_PORTH_RH3_POSITION | none | 0x3 |
_PORTH_RH3_SIZE | none | 0x1 |
_PORTH_RH3_LENGTH | none | 0x1 |
_PORTH_RH3_MASK | none | 0x8 |
_PORTH_RH4_POSN | none | 0x4 |
_PORTH_RH4_POSITION | none | 0x4 |
_PORTH_RH4_SIZE | none | 0x1 |
_PORTH_RH4_LENGTH | none | 0x1 |
_PORTH_RH4_MASK | none | 0x10 |
_PORTH_RH5_POSN | none | 0x5 |
_PORTH_RH5_POSITION | none | 0x5 |
_PORTH_RH5_SIZE | none | 0x1 |
_PORTH_RH5_LENGTH | none | 0x1 |
_PORTH_RH5_MASK | none | 0x20 |
_PORTH_RH6_POSN | none | 0x6 |
_PORTH_RH6_POSITION | none | 0x6 |
_PORTH_RH6_SIZE | none | 0x1 |
_PORTH_RH6_LENGTH | none | 0x1 |
_PORTH_RH6_MASK | none | 0x40 |
_PORTH_RH7_POSN | none | 0x7 |
_PORTH_RH7_POSITION | none | 0x7 |
_PORTH_RH7_SIZE | none | 0x1 |
_PORTH_RH7_LENGTH | none | 0x1 |
_PORTH_RH7_MASK | none | 0x80 |
_PORTH_A16_POSN | none | 0x0 |
_PORTH_A16_POSITION | none | 0x0 |
_PORTH_A16_SIZE | none | 0x1 |
_PORTH_A16_LENGTH | none | 0x1 |
_PORTH_A16_MASK | none | 0x1 |
_PORTH_A17_POSN | none | 0x1 |
_PORTH_A17_POSITION | none | 0x1 |
_PORTH_A17_SIZE | none | 0x1 |
_PORTH_A17_LENGTH | none | 0x1 |
_PORTH_A17_MASK | none | 0x2 |
_PORTH_A18_POSN | none | 0x2 |
_PORTH_A18_POSITION | none | 0x2 |
_PORTH_A18_SIZE | none | 0x1 |
_PORTH_A18_LENGTH | none | 0x1 |
_PORTH_A18_MASK | none | 0x4 |
_PORTH_A19_POSN | none | 0x3 |
_PORTH_A19_POSITION | none | 0x3 |
_PORTH_A19_SIZE | none | 0x1 |
_PORTH_A19_LENGTH | none | 0x1 |
_PORTH_A19_MASK | none | 0x8 |
_PORTH_AN12_POSN | none | 0x4 |
_PORTH_AN12_POSITION | none | 0x4 |
_PORTH_AN12_SIZE | none | 0x1 |
_PORTH_AN12_LENGTH | none | 0x1 |
_PORTH_AN12_MASK | none | 0x10 |
_PORTH_AN13_POSN | none | 0x5 |
_PORTH_AN13_POSITION | none | 0x5 |
_PORTH_AN13_SIZE | none | 0x1 |
_PORTH_AN13_LENGTH | none | 0x1 |
_PORTH_AN13_MASK | none | 0x20 |
_PORTH_AN14_POSN | none | 0x6 |
_PORTH_AN14_POSITION | none | 0x6 |
_PORTH_AN14_SIZE | none | 0x1 |
_PORTH_AN14_LENGTH | none | 0x1 |
_PORTH_AN14_MASK | none | 0x40 |
_PORTH_AN15_POSN | none | 0x7 |
_PORTH_AN15_POSITION | none | 0x7 |
_PORTH_AN15_SIZE | none | 0x1 |
_PORTH_AN15_LENGTH | none | 0x1 |
_PORTH_AN15_MASK | none | 0x80 |
_PORTH_AD16_POSN | none | 0x0 |
_PORTH_AD16_POSITION | none | 0x0 |
_PORTH_AD16_SIZE | none | 0x1 |
_PORTH_AD16_LENGTH | none | 0x1 |
_PORTH_AD16_MASK | none | 0x1 |
_PORTH_AD17_POSN | none | 0x1 |
_PORTH_AD17_POSITION | none | 0x1 |
_PORTH_AD17_SIZE | none | 0x1 |
_PORTH_AD17_LENGTH | none | 0x1 |
_PORTH_AD17_MASK | none | 0x2 |
_PORTH_AD18_POSN | none | 0x2 |
_PORTH_AD18_POSITION | none | 0x2 |
_PORTH_AD18_SIZE | none | 0x1 |
_PORTH_AD18_LENGTH | none | 0x1 |
_PORTH_AD18_MASK | none | 0x4 |
_PORTH_AD19_POSN | none | 0x3 |
_PORTH_AD19_POSITION | none | 0x3 |
_PORTH_AD19_SIZE | none | 0x1 |
_PORTH_AD19_LENGTH | none | 0x1 |
_PORTH_AD19_MASK | none | 0x8 |
_PORTH_CCP9_POSN | none | 0x4 |
_PORTH_CCP9_POSITION | none | 0x4 |
_PORTH_CCP9_SIZE | none | 0x1 |
_PORTH_CCP9_LENGTH | none | 0x1 |
_PORTH_CCP9_MASK | none | 0x10 |
_PORTH_CCP8_POSN | none | 0x5 |
_PORTH_CCP8_POSITION | none | 0x5 |
_PORTH_CCP8_SIZE | none | 0x1 |
_PORTH_CCP8_LENGTH | none | 0x1 |
_PORTH_CCP8_MASK | none | 0x20 |
_PORTH_CCP7_POSN | none | 0x6 |
_PORTH_CCP7_POSITION | none | 0x6 |
_PORTH_CCP7_SIZE | none | 0x1 |
_PORTH_CCP7_LENGTH | none | 0x1 |
_PORTH_CCP7_MASK | none | 0x40 |
_PORTH_CCP6_POSN | none | 0x7 |
_PORTH_CCP6_POSITION | none | 0x7 |
_PORTH_CCP6_SIZE | none | 0x1 |
_PORTH_CCP6_LENGTH | none | 0x1 |
_PORTH_CCP6_MASK | none | 0x80 |
_PORTH_PC3_POSN | none | 0x4 |
_PORTH_PC3_POSITION | none | 0x4 |
_PORTH_PC3_SIZE | none | 0x1 |
_PORTH_PC3_LENGTH | none | 0x1 |
_PORTH_PC3_MASK | none | 0x10 |
_PORTH_PB3_POSN | none | 0x5 |
_PORTH_PB3_POSITION | none | 0x5 |
_PORTH_PB3_SIZE | none | 0x1 |
_PORTH_PB3_LENGTH | none | 0x1 |
_PORTH_PB3_MASK | none | 0x20 |
_PORTH_PC1_POSN | none | 0x6 |
_PORTH_PC1_POSITION | none | 0x6 |
_PORTH_PC1_SIZE | none | 0x1 |
_PORTH_PC1_LENGTH | none | 0x1 |
_PORTH_PC1_MASK | none | 0x40 |
_PORTH_PB1_POSN | none | 0x7 |
_PORTH_PB1_POSITION | none | 0x7 |
_PORTH_PB1_SIZE | none | 0x1 |
_PORTH_PB1_LENGTH | none | 0x1 |
_PORTH_PB1_MASK | none | 0x80 |
PORTJ | none | <\077435>PORTJ |
PORTJ | none | <\077435>PORTJ |
_PORTJ_RJ0_POSN | none | 0x0 |
_PORTJ_RJ0_POSITION | none | 0x0 |
_PORTJ_RJ0_SIZE | none | 0x1 |
_PORTJ_RJ0_LENGTH | none | 0x1 |
_PORTJ_RJ0_MASK | none | 0x1 |
_PORTJ_RJ1_POSN | none | 0x1 |
_PORTJ_RJ1_POSITION | none | 0x1 |
_PORTJ_RJ1_SIZE | none | 0x1 |
_PORTJ_RJ1_LENGTH | none | 0x1 |
_PORTJ_RJ1_MASK | none | 0x2 |
_PORTJ_RJ2_POSN | none | 0x2 |
_PORTJ_RJ2_POSITION | none | 0x2 |
_PORTJ_RJ2_SIZE | none | 0x1 |
_PORTJ_RJ2_LENGTH | none | 0x1 |
_PORTJ_RJ2_MASK | none | 0x4 |
_PORTJ_RJ3_POSN | none | 0x3 |
_PORTJ_RJ3_POSITION | none | 0x3 |
_PORTJ_RJ3_SIZE | none | 0x1 |
_PORTJ_RJ3_LENGTH | none | 0x1 |
_PORTJ_RJ3_MASK | none | 0x8 |
_PORTJ_RJ4_POSN | none | 0x4 |
_PORTJ_RJ4_POSITION | none | 0x4 |
_PORTJ_RJ4_SIZE | none | 0x1 |
_PORTJ_RJ4_LENGTH | none | 0x1 |
_PORTJ_RJ4_MASK | none | 0x10 |
_PORTJ_RJ5_POSN | none | 0x5 |
_PORTJ_RJ5_POSITION | none | 0x5 |
_PORTJ_RJ5_SIZE | none | 0x1 |
_PORTJ_RJ5_LENGTH | none | 0x1 |
_PORTJ_RJ5_MASK | none | 0x20 |
_PORTJ_RJ6_POSN | none | 0x6 |
_PORTJ_RJ6_POSITION | none | 0x6 |
_PORTJ_RJ6_SIZE | none | 0x1 |
_PORTJ_RJ6_LENGTH | none | 0x1 |
_PORTJ_RJ6_MASK | none | 0x40 |
_PORTJ_RJ7_POSN | none | 0x7 |
_PORTJ_RJ7_POSITION | none | 0x7 |
_PORTJ_RJ7_SIZE | none | 0x1 |
_PORTJ_RJ7_LENGTH | none | 0x1 |
_PORTJ_RJ7_MASK | none | 0x80 |
_PORTJ_ALE_POSN | none | 0x0 |
_PORTJ_ALE_POSITION | none | 0x0 |
_PORTJ_ALE_SIZE | none | 0x1 |
_PORTJ_ALE_LENGTH | none | 0x1 |
_PORTJ_ALE_MASK | none | 0x1 |
_PORTJ_OE_POSN | none | 0x1 |
_PORTJ_OE_POSITION | none | 0x1 |
_PORTJ_OE_SIZE | none | 0x1 |
_PORTJ_OE_LENGTH | none | 0x1 |
_PORTJ_OE_MASK | none | 0x2 |
_PORTJ_WRL_POSN | none | 0x2 |
_PORTJ_WRL_POSITION | none | 0x2 |
_PORTJ_WRL_SIZE | none | 0x1 |
_PORTJ_WRL_LENGTH | none | 0x1 |
_PORTJ_WRL_MASK | none | 0x4 |
_PORTJ_WRH_POSN | none | 0x3 |
_PORTJ_WRH_POSITION | none | 0x3 |
_PORTJ_WRH_SIZE | none | 0x1 |
_PORTJ_WRH_LENGTH | none | 0x1 |
_PORTJ_WRH_MASK | none | 0x8 |
_PORTJ_BA0_POSN | none | 0x4 |
_PORTJ_BA0_POSITION | none | 0x4 |
_PORTJ_BA0_SIZE | none | 0x1 |
_PORTJ_BA0_LENGTH | none | 0x1 |
_PORTJ_BA0_MASK | none | 0x10 |
_PORTJ_CE_POSN | none | 0x5 |
_PORTJ_CE_POSITION | none | 0x5 |
_PORTJ_CE_SIZE | none | 0x1 |
_PORTJ_CE_LENGTH | none | 0x1 |
_PORTJ_CE_MASK | none | 0x20 |
_PORTJ_LB_POSN | none | 0x6 |
_PORTJ_LB_POSITION | none | 0x6 |
_PORTJ_LB_SIZE | none | 0x1 |
_PORTJ_LB_LENGTH | none | 0x1 |
_PORTJ_LB_MASK | none | 0x40 |
_PORTJ_UB_POSN | none | 0x7 |
_PORTJ_UB_POSITION | none | 0x7 |
_PORTJ_UB_SIZE | none | 0x1 |
_PORTJ_UB_LENGTH | none | 0x1 |
_PORTJ_UB_MASK | none | 0x80 |
LATA | none | <\077435>LATA |
LATA | none | <\077435>LATA |
_LATA_LATA0_POSN | none | 0x0 |
_LATA_LATA0_POSITION | none | 0x0 |
_LATA_LATA0_SIZE | none | 0x1 |
_LATA_LATA0_LENGTH | none | 0x1 |
_LATA_LATA0_MASK | none | 0x1 |
_LATA_LATA1_POSN | none | 0x1 |
_LATA_LATA1_POSITION | none | 0x1 |
_LATA_LATA1_SIZE | none | 0x1 |
_LATA_LATA1_LENGTH | none | 0x1 |
_LATA_LATA1_MASK | none | 0x2 |
_LATA_LATA2_POSN | none | 0x2 |
_LATA_LATA2_POSITION | none | 0x2 |
_LATA_LATA2_SIZE | none | 0x1 |
_LATA_LATA2_LENGTH | none | 0x1 |
_LATA_LATA2_MASK | none | 0x4 |
_LATA_LATA3_POSN | none | 0x3 |
_LATA_LATA3_POSITION | none | 0x3 |
_LATA_LATA3_SIZE | none | 0x1 |
_LATA_LATA3_LENGTH | none | 0x1 |
_LATA_LATA3_MASK | none | 0x8 |
_LATA_LATA4_POSN | none | 0x4 |
_LATA_LATA4_POSITION | none | 0x4 |
_LATA_LATA4_SIZE | none | 0x1 |
_LATA_LATA4_LENGTH | none | 0x1 |
_LATA_LATA4_MASK | none | 0x10 |
_LATA_LATA5_POSN | none | 0x5 |
_LATA_LATA5_POSITION | none | 0x5 |
_LATA_LATA5_SIZE | none | 0x1 |
_LATA_LATA5_LENGTH | none | 0x1 |
_LATA_LATA5_MASK | none | 0x20 |
_LATA_LATA6_POSN | none | 0x6 |
_LATA_LATA6_POSITION | none | 0x6 |
_LATA_LATA6_SIZE | none | 0x1 |
_LATA_LATA6_LENGTH | none | 0x1 |
_LATA_LATA6_MASK | none | 0x40 |
_LATA_LA0_POSN | none | 0x0 |
_LATA_LA0_POSITION | none | 0x0 |
_LATA_LA0_SIZE | none | 0x1 |
_LATA_LA0_LENGTH | none | 0x1 |
_LATA_LA0_MASK | none | 0x1 |
_LATA_LA1_POSN | none | 0x1 |
_LATA_LA1_POSITION | none | 0x1 |
_LATA_LA1_SIZE | none | 0x1 |
_LATA_LA1_LENGTH | none | 0x1 |
_LATA_LA1_MASK | none | 0x2 |
_LATA_LA2_POSN | none | 0x2 |
_LATA_LA2_POSITION | none | 0x2 |
_LATA_LA2_SIZE | none | 0x1 |
_LATA_LA2_LENGTH | none | 0x1 |
_LATA_LA2_MASK | none | 0x4 |
_LATA_LA3_POSN | none | 0x3 |
_LATA_LA3_POSITION | none | 0x3 |
_LATA_LA3_SIZE | none | 0x1 |
_LATA_LA3_LENGTH | none | 0x1 |
_LATA_LA3_MASK | none | 0x8 |
_LATA_LA4_POSN | none | 0x4 |
_LATA_LA4_POSITION | none | 0x4 |
_LATA_LA4_SIZE | none | 0x1 |
_LATA_LA4_LENGTH | none | 0x1 |
_LATA_LA4_MASK | none | 0x10 |
_LATA_LA5_POSN | none | 0x5 |
_LATA_LA5_POSITION | none | 0x5 |
_LATA_LA5_SIZE | none | 0x1 |
_LATA_LA5_LENGTH | none | 0x1 |
_LATA_LA5_MASK | none | 0x20 |
_LATA_LA6_POSN | none | 0x6 |
_LATA_LA6_POSITION | none | 0x6 |
_LATA_LA6_SIZE | none | 0x1 |
_LATA_LA6_LENGTH | none | 0x1 |
_LATA_LA6_MASK | none | 0x40 |
LATB | none | <\077435>LATB |
LATB | none | <\077435>LATB |
_LATB_LATB0_POSN | none | 0x0 |
_LATB_LATB0_POSITION | none | 0x0 |
_LATB_LATB0_SIZE | none | 0x1 |
_LATB_LATB0_LENGTH | none | 0x1 |
_LATB_LATB0_MASK | none | 0x1 |
_LATB_LATB1_POSN | none | 0x1 |
_LATB_LATB1_POSITION | none | 0x1 |
_LATB_LATB1_SIZE | none | 0x1 |
_LATB_LATB1_LENGTH | none | 0x1 |
_LATB_LATB1_MASK | none | 0x2 |
_LATB_LATB2_POSN | none | 0x2 |
_LATB_LATB2_POSITION | none | 0x2 |
_LATB_LATB2_SIZE | none | 0x1 |
_LATB_LATB2_LENGTH | none | 0x1 |
_LATB_LATB2_MASK | none | 0x4 |
_LATB_LATB3_POSN | none | 0x3 |
_LATB_LATB3_POSITION | none | 0x3 |
_LATB_LATB3_SIZE | none | 0x1 |
_LATB_LATB3_LENGTH | none | 0x1 |
_LATB_LATB3_MASK | none | 0x8 |
_LATB_LATB4_POSN | none | 0x4 |
_LATB_LATB4_POSITION | none | 0x4 |
_LATB_LATB4_SIZE | none | 0x1 |
_LATB_LATB4_LENGTH | none | 0x1 |
_LATB_LATB4_MASK | none | 0x10 |
_LATB_LATB5_POSN | none | 0x5 |
_LATB_LATB5_POSITION | none | 0x5 |
_LATB_LATB5_SIZE | none | 0x1 |
_LATB_LATB5_LENGTH | none | 0x1 |
_LATB_LATB5_MASK | none | 0x20 |
_LATB_LATB6_POSN | none | 0x6 |
_LATB_LATB6_POSITION | none | 0x6 |
_LATB_LATB6_SIZE | none | 0x1 |
_LATB_LATB6_LENGTH | none | 0x1 |
_LATB_LATB6_MASK | none | 0x40 |
_LATB_LATB7_POSN | none | 0x7 |
_LATB_LATB7_POSITION | none | 0x7 |
_LATB_LATB7_SIZE | none | 0x1 |
_LATB_LATB7_LENGTH | none | 0x1 |
_LATB_LATB7_MASK | none | 0x80 |
_LATB_LB0_POSN | none | 0x0 |
_LATB_LB0_POSITION | none | 0x0 |
_LATB_LB0_SIZE | none | 0x1 |
_LATB_LB0_LENGTH | none | 0x1 |
_LATB_LB0_MASK | none | 0x1 |
_LATB_LB1_POSN | none | 0x1 |
_LATB_LB1_POSITION | none | 0x1 |
_LATB_LB1_SIZE | none | 0x1 |
_LATB_LB1_LENGTH | none | 0x1 |
_LATB_LB1_MASK | none | 0x2 |
_LATB_LB2_POSN | none | 0x2 |
_LATB_LB2_POSITION | none | 0x2 |
_LATB_LB2_SIZE | none | 0x1 |
_LATB_LB2_LENGTH | none | 0x1 |
_LATB_LB2_MASK | none | 0x4 |
_LATB_LB3_POSN | none | 0x3 |
_LATB_LB3_POSITION | none | 0x3 |
_LATB_LB3_SIZE | none | 0x1 |
_LATB_LB3_LENGTH | none | 0x1 |
_LATB_LB3_MASK | none | 0x8 |
_LATB_LB4_POSN | none | 0x4 |
_LATB_LB4_POSITION | none | 0x4 |
_LATB_LB4_SIZE | none | 0x1 |
_LATB_LB4_LENGTH | none | 0x1 |
_LATB_LB4_MASK | none | 0x10 |
_LATB_LB5_POSN | none | 0x5 |
_LATB_LB5_POSITION | none | 0x5 |
_LATB_LB5_SIZE | none | 0x1 |
_LATB_LB5_LENGTH | none | 0x1 |
_LATB_LB5_MASK | none | 0x20 |
_LATB_LB6_POSN | none | 0x6 |
_LATB_LB6_POSITION | none | 0x6 |
_LATB_LB6_SIZE | none | 0x1 |
_LATB_LB6_LENGTH | none | 0x1 |
_LATB_LB6_MASK | none | 0x40 |
_LATB_LB7_POSN | none | 0x7 |
_LATB_LB7_POSITION | none | 0x7 |
_LATB_LB7_SIZE | none | 0x1 |
_LATB_LB7_LENGTH | none | 0x1 |
_LATB_LB7_MASK | none | 0x80 |
LATC | none | <\077435>LATC |
LATC | none | <\077435>LATC |
_LATC_LATC0_POSN | none | 0x0 |
_LATC_LATC0_POSITION | none | 0x0 |
_LATC_LATC0_SIZE | none | 0x1 |
_LATC_LATC0_LENGTH | none | 0x1 |
_LATC_LATC0_MASK | none | 0x1 |
_LATC_LATC1_POSN | none | 0x1 |
_LATC_LATC1_POSITION | none | 0x1 |
_LATC_LATC1_SIZE | none | 0x1 |
_LATC_LATC1_LENGTH | none | 0x1 |
_LATC_LATC1_MASK | none | 0x2 |
_LATC_LATC2_POSN | none | 0x2 |
_LATC_LATC2_POSITION | none | 0x2 |
_LATC_LATC2_SIZE | none | 0x1 |
_LATC_LATC2_LENGTH | none | 0x1 |
_LATC_LATC2_MASK | none | 0x4 |
_LATC_LATC3_POSN | none | 0x3 |
_LATC_LATC3_POSITION | none | 0x3 |
_LATC_LATC3_SIZE | none | 0x1 |
_LATC_LATC3_LENGTH | none | 0x1 |
_LATC_LATC3_MASK | none | 0x8 |
_LATC_LATC4_POSN | none | 0x4 |
_LATC_LATC4_POSITION | none | 0x4 |
_LATC_LATC4_SIZE | none | 0x1 |
_LATC_LATC4_LENGTH | none | 0x1 |
_LATC_LATC4_MASK | none | 0x10 |
_LATC_LATC5_POSN | none | 0x5 |
_LATC_LATC5_POSITION | none | 0x5 |
_LATC_LATC5_SIZE | none | 0x1 |
_LATC_LATC5_LENGTH | none | 0x1 |
_LATC_LATC5_MASK | none | 0x20 |
_LATC_LATC6_POSN | none | 0x6 |
_LATC_LATC6_POSITION | none | 0x6 |
_LATC_LATC6_SIZE | none | 0x1 |
_LATC_LATC6_LENGTH | none | 0x1 |
_LATC_LATC6_MASK | none | 0x40 |
_LATC_LATC7_POSN | none | 0x7 |
_LATC_LATC7_POSITION | none | 0x7 |
_LATC_LATC7_SIZE | none | 0x1 |
_LATC_LATC7_LENGTH | none | 0x1 |
_LATC_LATC7_MASK | none | 0x80 |
_LATC_LC0_POSN | none | 0x0 |
_LATC_LC0_POSITION | none | 0x0 |
_LATC_LC0_SIZE | none | 0x1 |
_LATC_LC0_LENGTH | none | 0x1 |
_LATC_LC0_MASK | none | 0x1 |
_LATC_LC1_POSN | none | 0x1 |
_LATC_LC1_POSITION | none | 0x1 |
_LATC_LC1_SIZE | none | 0x1 |
_LATC_LC1_LENGTH | none | 0x1 |
_LATC_LC1_MASK | none | 0x2 |
_LATC_LC2_POSN | none | 0x2 |
_LATC_LC2_POSITION | none | 0x2 |
_LATC_LC2_SIZE | none | 0x1 |
_LATC_LC2_LENGTH | none | 0x1 |
_LATC_LC2_MASK | none | 0x4 |
_LATC_LC3_POSN | none | 0x3 |
_LATC_LC3_POSITION | none | 0x3 |
_LATC_LC3_SIZE | none | 0x1 |
_LATC_LC3_LENGTH | none | 0x1 |
_LATC_LC3_MASK | none | 0x8 |
_LATC_LC4_POSN | none | 0x4 |
_LATC_LC4_POSITION | none | 0x4 |
_LATC_LC4_SIZE | none | 0x1 |
_LATC_LC4_LENGTH | none | 0x1 |
_LATC_LC4_MASK | none | 0x10 |
_LATC_LC5_POSN | none | 0x5 |
_LATC_LC5_POSITION | none | 0x5 |
_LATC_LC5_SIZE | none | 0x1 |
_LATC_LC5_LENGTH | none | 0x1 |
_LATC_LC5_MASK | none | 0x20 |
_LATC_LC6_POSN | none | 0x6 |
_LATC_LC6_POSITION | none | 0x6 |
_LATC_LC6_SIZE | none | 0x1 |
_LATC_LC6_LENGTH | none | 0x1 |
_LATC_LC6_MASK | none | 0x40 |
_LATC_LC7_POSN | none | 0x7 |
_LATC_LC7_POSITION | none | 0x7 |
_LATC_LC7_SIZE | none | 0x1 |
_LATC_LC7_LENGTH | none | 0x1 |
_LATC_LC7_MASK | none | 0x80 |
LATD | none | <\077435>LATD |
LATD | none | <\077435>LATD |
_LATD_LATD0_POSN | none | 0x0 |
_LATD_LATD0_POSITION | none | 0x0 |
_LATD_LATD0_SIZE | none | 0x1 |
_LATD_LATD0_LENGTH | none | 0x1 |
_LATD_LATD0_MASK | none | 0x1 |
_LATD_LATD1_POSN | none | 0x1 |
_LATD_LATD1_POSITION | none | 0x1 |
_LATD_LATD1_SIZE | none | 0x1 |
_LATD_LATD1_LENGTH | none | 0x1 |
_LATD_LATD1_MASK | none | 0x2 |
_LATD_LATD2_POSN | none | 0x2 |
_LATD_LATD2_POSITION | none | 0x2 |
_LATD_LATD2_SIZE | none | 0x1 |
_LATD_LATD2_LENGTH | none | 0x1 |
_LATD_LATD2_MASK | none | 0x4 |
_LATD_LATD3_POSN | none | 0x3 |
_LATD_LATD3_POSITION | none | 0x3 |
_LATD_LATD3_SIZE | none | 0x1 |
_LATD_LATD3_LENGTH | none | 0x1 |
_LATD_LATD3_MASK | none | 0x8 |
_LATD_LATD4_POSN | none | 0x4 |
_LATD_LATD4_POSITION | none | 0x4 |
_LATD_LATD4_SIZE | none | 0x1 |
_LATD_LATD4_LENGTH | none | 0x1 |
_LATD_LATD4_MASK | none | 0x10 |
_LATD_LATD5_POSN | none | 0x5 |
_LATD_LATD5_POSITION | none | 0x5 |
_LATD_LATD5_SIZE | none | 0x1 |
_LATD_LATD5_LENGTH | none | 0x1 |
_LATD_LATD5_MASK | none | 0x20 |
_LATD_LATD6_POSN | none | 0x6 |
_LATD_LATD6_POSITION | none | 0x6 |
_LATD_LATD6_SIZE | none | 0x1 |
_LATD_LATD6_LENGTH | none | 0x1 |
_LATD_LATD6_MASK | none | 0x40 |
_LATD_LATD7_POSN | none | 0x7 |
_LATD_LATD7_POSITION | none | 0x7 |
_LATD_LATD7_SIZE | none | 0x1 |
_LATD_LATD7_LENGTH | none | 0x1 |
_LATD_LATD7_MASK | none | 0x80 |
_LATD_LD0_POSN | none | 0x0 |
_LATD_LD0_POSITION | none | 0x0 |
_LATD_LD0_SIZE | none | 0x1 |
_LATD_LD0_LENGTH | none | 0x1 |
_LATD_LD0_MASK | none | 0x1 |
_LATD_LD1_POSN | none | 0x1 |
_LATD_LD1_POSITION | none | 0x1 |
_LATD_LD1_SIZE | none | 0x1 |
_LATD_LD1_LENGTH | none | 0x1 |
_LATD_LD1_MASK | none | 0x2 |
_LATD_LD2_POSN | none | 0x2 |
_LATD_LD2_POSITION | none | 0x2 |
_LATD_LD2_SIZE | none | 0x1 |
_LATD_LD2_LENGTH | none | 0x1 |
_LATD_LD2_MASK | none | 0x4 |
_LATD_LD3_POSN | none | 0x3 |
_LATD_LD3_POSITION | none | 0x3 |
_LATD_LD3_SIZE | none | 0x1 |
_LATD_LD3_LENGTH | none | 0x1 |
_LATD_LD3_MASK | none | 0x8 |
_LATD_LD4_POSN | none | 0x4 |
_LATD_LD4_POSITION | none | 0x4 |
_LATD_LD4_SIZE | none | 0x1 |
_LATD_LD4_LENGTH | none | 0x1 |
_LATD_LD4_MASK | none | 0x10 |
_LATD_LD5_POSN | none | 0x5 |
_LATD_LD5_POSITION | none | 0x5 |
_LATD_LD5_SIZE | none | 0x1 |
_LATD_LD5_LENGTH | none | 0x1 |
_LATD_LD5_MASK | none | 0x20 |
_LATD_LD6_POSN | none | 0x6 |
_LATD_LD6_POSITION | none | 0x6 |
_LATD_LD6_SIZE | none | 0x1 |
_LATD_LD6_LENGTH | none | 0x1 |
_LATD_LD6_MASK | none | 0x40 |
_LATD_LD7_POSN | none | 0x7 |
_LATD_LD7_POSITION | none | 0x7 |
_LATD_LD7_SIZE | none | 0x1 |
_LATD_LD7_LENGTH | none | 0x1 |
_LATD_LD7_MASK | none | 0x80 |
LATE | none | <\077435>LATE |
LATE | none | <\077435>LATE |
_LATE_LATE0_POSN | none | 0x0 |
_LATE_LATE0_POSITION | none | 0x0 |
_LATE_LATE0_SIZE | none | 0x1 |
_LATE_LATE0_LENGTH | none | 0x1 |
_LATE_LATE0_MASK | none | 0x1 |
_LATE_LATE1_POSN | none | 0x1 |
_LATE_LATE1_POSITION | none | 0x1 |
_LATE_LATE1_SIZE | none | 0x1 |
_LATE_LATE1_LENGTH | none | 0x1 |
_LATE_LATE1_MASK | none | 0x2 |
_LATE_LATE2_POSN | none | 0x2 |
_LATE_LATE2_POSITION | none | 0x2 |
_LATE_LATE2_SIZE | none | 0x1 |
_LATE_LATE2_LENGTH | none | 0x1 |
_LATE_LATE2_MASK | none | 0x4 |
_LATE_LATE3_POSN | none | 0x3 |
_LATE_LATE3_POSITION | none | 0x3 |
_LATE_LATE3_SIZE | none | 0x1 |
_LATE_LATE3_LENGTH | none | 0x1 |
_LATE_LATE3_MASK | none | 0x8 |
_LATE_LATE4_POSN | none | 0x4 |
_LATE_LATE4_POSITION | none | 0x4 |
_LATE_LATE4_SIZE | none | 0x1 |
_LATE_LATE4_LENGTH | none | 0x1 |
_LATE_LATE4_MASK | none | 0x10 |
_LATE_LATE5_POSN | none | 0x5 |
_LATE_LATE5_POSITION | none | 0x5 |
_LATE_LATE5_SIZE | none | 0x1 |
_LATE_LATE5_LENGTH | none | 0x1 |
_LATE_LATE5_MASK | none | 0x20 |
_LATE_LATE6_POSN | none | 0x6 |
_LATE_LATE6_POSITION | none | 0x6 |
_LATE_LATE6_SIZE | none | 0x1 |
_LATE_LATE6_LENGTH | none | 0x1 |
_LATE_LATE6_MASK | none | 0x40 |
_LATE_LATE7_POSN | none | 0x7 |
_LATE_LATE7_POSITION | none | 0x7 |
_LATE_LATE7_SIZE | none | 0x1 |
_LATE_LATE7_LENGTH | none | 0x1 |
_LATE_LATE7_MASK | none | 0x80 |
_LATE_LE0_POSN | none | 0x0 |
_LATE_LE0_POSITION | none | 0x0 |
_LATE_LE0_SIZE | none | 0x1 |
_LATE_LE0_LENGTH | none | 0x1 |
_LATE_LE0_MASK | none | 0x1 |
_LATE_LE1_POSN | none | 0x1 |
_LATE_LE1_POSITION | none | 0x1 |
_LATE_LE1_SIZE | none | 0x1 |
_LATE_LE1_LENGTH | none | 0x1 |
_LATE_LE1_MASK | none | 0x2 |
_LATE_LE2_POSN | none | 0x2 |
_LATE_LE2_POSITION | none | 0x2 |
_LATE_LE2_SIZE | none | 0x1 |
_LATE_LE2_LENGTH | none | 0x1 |
_LATE_LE2_MASK | none | 0x4 |
_LATE_LE3_POSN | none | 0x3 |
_LATE_LE3_POSITION | none | 0x3 |
_LATE_LE3_SIZE | none | 0x1 |
_LATE_LE3_LENGTH | none | 0x1 |
_LATE_LE3_MASK | none | 0x8 |
_LATE_LE4_POSN | none | 0x4 |
_LATE_LE4_POSITION | none | 0x4 |
_LATE_LE4_SIZE | none | 0x1 |
_LATE_LE4_LENGTH | none | 0x1 |
_LATE_LE4_MASK | none | 0x10 |
_LATE_LE5_POSN | none | 0x5 |
_LATE_LE5_POSITION | none | 0x5 |
_LATE_LE5_SIZE | none | 0x1 |
_LATE_LE5_LENGTH | none | 0x1 |
_LATE_LE5_MASK | none | 0x20 |
_LATE_LE6_POSN | none | 0x6 |
_LATE_LE6_POSITION | none | 0x6 |
_LATE_LE6_SIZE | none | 0x1 |
_LATE_LE6_LENGTH | none | 0x1 |
_LATE_LE6_MASK | none | 0x40 |
_LATE_LE7_POSN | none | 0x7 |
_LATE_LE7_POSITION | none | 0x7 |
_LATE_LE7_SIZE | none | 0x1 |
_LATE_LE7_LENGTH | none | 0x1 |
_LATE_LE7_MASK | none | 0x80 |
LATF | none | <\077435>LATF |
LATF | none | <\077435>LATF |
_LATF_LATF0_POSN | none | 0x0 |
_LATF_LATF0_POSITION | none | 0x0 |
_LATF_LATF0_SIZE | none | 0x1 |
_LATF_LATF0_LENGTH | none | 0x1 |
_LATF_LATF0_MASK | none | 0x1 |
_LATF_LATF1_POSN | none | 0x1 |
_LATF_LATF1_POSITION | none | 0x1 |
_LATF_LATF1_SIZE | none | 0x1 |
_LATF_LATF1_LENGTH | none | 0x1 |
_LATF_LATF1_MASK | none | 0x2 |
_LATF_LATF2_POSN | none | 0x2 |
_LATF_LATF2_POSITION | none | 0x2 |
_LATF_LATF2_SIZE | none | 0x1 |
_LATF_LATF2_LENGTH | none | 0x1 |
_LATF_LATF2_MASK | none | 0x4 |
_LATF_LATF3_POSN | none | 0x3 |
_LATF_LATF3_POSITION | none | 0x3 |
_LATF_LATF3_SIZE | none | 0x1 |
_LATF_LATF3_LENGTH | none | 0x1 |
_LATF_LATF3_MASK | none | 0x8 |
_LATF_LATF4_POSN | none | 0x4 |
_LATF_LATF4_POSITION | none | 0x4 |
_LATF_LATF4_SIZE | none | 0x1 |
_LATF_LATF4_LENGTH | none | 0x1 |
_LATF_LATF4_MASK | none | 0x10 |
_LATF_LATF5_POSN | none | 0x5 |
_LATF_LATF5_POSITION | none | 0x5 |
_LATF_LATF5_SIZE | none | 0x1 |
_LATF_LATF5_LENGTH | none | 0x1 |
_LATF_LATF5_MASK | none | 0x20 |
_LATF_LATF6_POSN | none | 0x6 |
_LATF_LATF6_POSITION | none | 0x6 |
_LATF_LATF6_SIZE | none | 0x1 |
_LATF_LATF6_LENGTH | none | 0x1 |
_LATF_LATF6_MASK | none | 0x40 |
_LATF_LATF7_POSN | none | 0x7 |
_LATF_LATF7_POSITION | none | 0x7 |
_LATF_LATF7_SIZE | none | 0x1 |
_LATF_LATF7_LENGTH | none | 0x1 |
_LATF_LATF7_MASK | none | 0x80 |
_LATF_LF0_POSN | none | 0x0 |
_LATF_LF0_POSITION | none | 0x0 |
_LATF_LF0_SIZE | none | 0x1 |
_LATF_LF0_LENGTH | none | 0x1 |
_LATF_LF0_MASK | none | 0x1 |
_LATF_LF1_POSN | none | 0x1 |
_LATF_LF1_POSITION | none | 0x1 |
_LATF_LF1_SIZE | none | 0x1 |
_LATF_LF1_LENGTH | none | 0x1 |
_LATF_LF1_MASK | none | 0x2 |
_LATF_LF2_POSN | none | 0x2 |
_LATF_LF2_POSITION | none | 0x2 |
_LATF_LF2_SIZE | none | 0x1 |
_LATF_LF2_LENGTH | none | 0x1 |
_LATF_LF2_MASK | none | 0x4 |
_LATF_LF3_POSN | none | 0x3 |
_LATF_LF3_POSITION | none | 0x3 |
_LATF_LF3_SIZE | none | 0x1 |
_LATF_LF3_LENGTH | none | 0x1 |
_LATF_LF3_MASK | none | 0x8 |
_LATF_LF4_POSN | none | 0x4 |
_LATF_LF4_POSITION | none | 0x4 |
_LATF_LF4_SIZE | none | 0x1 |
_LATF_LF4_LENGTH | none | 0x1 |
_LATF_LF4_MASK | none | 0x10 |
_LATF_LF5_POSN | none | 0x5 |
_LATF_LF5_POSITION | none | 0x5 |
_LATF_LF5_SIZE | none | 0x1 |
_LATF_LF5_LENGTH | none | 0x1 |
_LATF_LF5_MASK | none | 0x20 |
_LATF_LF6_POSN | none | 0x6 |
_LATF_LF6_POSITION | none | 0x6 |
_LATF_LF6_SIZE | none | 0x1 |
_LATF_LF6_LENGTH | none | 0x1 |
_LATF_LF6_MASK | none | 0x40 |
_LATF_LF7_POSN | none | 0x7 |
_LATF_LF7_POSITION | none | 0x7 |
_LATF_LF7_SIZE | none | 0x1 |
_LATF_LF7_LENGTH | none | 0x1 |
_LATF_LF7_MASK | none | 0x80 |
LATG | none | <\077435>LATG |
LATG | none | <\077435>LATG |
_LATG_LATG0_POSN | none | 0x0 |
_LATG_LATG0_POSITION | none | 0x0 |
_LATG_LATG0_SIZE | none | 0x1 |
_LATG_LATG0_LENGTH | none | 0x1 |
_LATG_LATG0_MASK | none | 0x1 |
_LATG_LATG1_POSN | none | 0x1 |
_LATG_LATG1_POSITION | none | 0x1 |
_LATG_LATG1_SIZE | none | 0x1 |
_LATG_LATG1_LENGTH | none | 0x1 |
_LATG_LATG1_MASK | none | 0x2 |
_LATG_LATG2_POSN | none | 0x2 |
_LATG_LATG2_POSITION | none | 0x2 |
_LATG_LATG2_SIZE | none | 0x1 |
_LATG_LATG2_LENGTH | none | 0x1 |
_LATG_LATG2_MASK | none | 0x4 |
_LATG_LATG3_POSN | none | 0x3 |
_LATG_LATG3_POSITION | none | 0x3 |
_LATG_LATG3_SIZE | none | 0x1 |
_LATG_LATG3_LENGTH | none | 0x1 |
_LATG_LATG3_MASK | none | 0x8 |
_LATG_LATG4_POSN | none | 0x4 |
_LATG_LATG4_POSITION | none | 0x4 |
_LATG_LATG4_SIZE | none | 0x1 |
_LATG_LATG4_LENGTH | none | 0x1 |
_LATG_LATG4_MASK | none | 0x10 |
_LATG_LG0_POSN | none | 0x0 |
_LATG_LG0_POSITION | none | 0x0 |
_LATG_LG0_SIZE | none | 0x1 |
_LATG_LG0_LENGTH | none | 0x1 |
_LATG_LG0_MASK | none | 0x1 |
_LATG_LG1_POSN | none | 0x1 |
_LATG_LG1_POSITION | none | 0x1 |
_LATG_LG1_SIZE | none | 0x1 |
_LATG_LG1_LENGTH | none | 0x1 |
_LATG_LG1_MASK | none | 0x2 |
_LATG_LG2_POSN | none | 0x2 |
_LATG_LG2_POSITION | none | 0x2 |
_LATG_LG2_SIZE | none | 0x1 |
_LATG_LG2_LENGTH | none | 0x1 |
_LATG_LG2_MASK | none | 0x4 |
_LATG_LG3_POSN | none | 0x3 |
_LATG_LG3_POSITION | none | 0x3 |
_LATG_LG3_SIZE | none | 0x1 |
_LATG_LG3_LENGTH | none | 0x1 |
_LATG_LG3_MASK | none | 0x8 |
_LATG_LG4_POSN | none | 0x4 |
_LATG_LG4_POSITION | none | 0x4 |
_LATG_LG4_SIZE | none | 0x1 |
_LATG_LG4_LENGTH | none | 0x1 |
_LATG_LG4_MASK | none | 0x10 |
LATH | none | <\077435>LATH |
LATH | none | <\077435>LATH |
_LATH_LATH0_POSN | none | 0x0 |
_LATH_LATH0_POSITION | none | 0x0 |
_LATH_LATH0_SIZE | none | 0x1 |
_LATH_LATH0_LENGTH | none | 0x1 |
_LATH_LATH0_MASK | none | 0x1 |
_LATH_LATH1_POSN | none | 0x1 |
_LATH_LATH1_POSITION | none | 0x1 |
_LATH_LATH1_SIZE | none | 0x1 |
_LATH_LATH1_LENGTH | none | 0x1 |
_LATH_LATH1_MASK | none | 0x2 |
_LATH_LATH2_POSN | none | 0x2 |
_LATH_LATH2_POSITION | none | 0x2 |
_LATH_LATH2_SIZE | none | 0x1 |
_LATH_LATH2_LENGTH | none | 0x1 |
_LATH_LATH2_MASK | none | 0x4 |
_LATH_LATH3_POSN | none | 0x3 |
_LATH_LATH3_POSITION | none | 0x3 |
_LATH_LATH3_SIZE | none | 0x1 |
_LATH_LATH3_LENGTH | none | 0x1 |
_LATH_LATH3_MASK | none | 0x8 |
_LATH_LATH4_POSN | none | 0x4 |
_LATH_LATH4_POSITION | none | 0x4 |
_LATH_LATH4_SIZE | none | 0x1 |
_LATH_LATH4_LENGTH | none | 0x1 |
_LATH_LATH4_MASK | none | 0x10 |
_LATH_LATH5_POSN | none | 0x5 |
_LATH_LATH5_POSITION | none | 0x5 |
_LATH_LATH5_SIZE | none | 0x1 |
_LATH_LATH5_LENGTH | none | 0x1 |
_LATH_LATH5_MASK | none | 0x20 |
_LATH_LATH6_POSN | none | 0x6 |
_LATH_LATH6_POSITION | none | 0x6 |
_LATH_LATH6_SIZE | none | 0x1 |
_LATH_LATH6_LENGTH | none | 0x1 |
_LATH_LATH6_MASK | none | 0x40 |
_LATH_LATH7_POSN | none | 0x7 |
_LATH_LATH7_POSITION | none | 0x7 |
_LATH_LATH7_SIZE | none | 0x1 |
_LATH_LATH7_LENGTH | none | 0x1 |
_LATH_LATH7_MASK | none | 0x80 |
_LATH_LH0_POSN | none | 0x0 |
_LATH_LH0_POSITION | none | 0x0 |
_LATH_LH0_SIZE | none | 0x1 |
_LATH_LH0_LENGTH | none | 0x1 |
_LATH_LH0_MASK | none | 0x1 |
_LATH_LH1_POSN | none | 0x1 |
_LATH_LH1_POSITION | none | 0x1 |
_LATH_LH1_SIZE | none | 0x1 |
_LATH_LH1_LENGTH | none | 0x1 |
_LATH_LH1_MASK | none | 0x2 |
_LATH_LH2_POSN | none | 0x2 |
_LATH_LH2_POSITION | none | 0x2 |
_LATH_LH2_SIZE | none | 0x1 |
_LATH_LH2_LENGTH | none | 0x1 |
_LATH_LH2_MASK | none | 0x4 |
_LATH_LH3_POSN | none | 0x3 |
_LATH_LH3_POSITION | none | 0x3 |
_LATH_LH3_SIZE | none | 0x1 |
_LATH_LH3_LENGTH | none | 0x1 |
_LATH_LH3_MASK | none | 0x8 |
_LATH_LH4_POSN | none | 0x4 |
_LATH_LH4_POSITION | none | 0x4 |
_LATH_LH4_SIZE | none | 0x1 |
_LATH_LH4_LENGTH | none | 0x1 |
_LATH_LH4_MASK | none | 0x10 |
_LATH_LH5_POSN | none | 0x5 |
_LATH_LH5_POSITION | none | 0x5 |
_LATH_LH5_SIZE | none | 0x1 |
_LATH_LH5_LENGTH | none | 0x1 |
_LATH_LH5_MASK | none | 0x20 |
_LATH_LH6_POSN | none | 0x6 |
_LATH_LH6_POSITION | none | 0x6 |
_LATH_LH6_SIZE | none | 0x1 |
_LATH_LH6_LENGTH | none | 0x1 |
_LATH_LH6_MASK | none | 0x40 |
_LATH_LH7_POSN | none | 0x7 |
_LATH_LH7_POSITION | none | 0x7 |
_LATH_LH7_SIZE | none | 0x1 |
_LATH_LH7_LENGTH | none | 0x1 |
_LATH_LH7_MASK | none | 0x80 |
LATJ | none | <\077435>LATJ |
LATJ | none | <\077435>LATJ |
_LATJ_LATJ0_POSN | none | 0x0 |
_LATJ_LATJ0_POSITION | none | 0x0 |
_LATJ_LATJ0_SIZE | none | 0x1 |
_LATJ_LATJ0_LENGTH | none | 0x1 |
_LATJ_LATJ0_MASK | none | 0x1 |
_LATJ_LATJ1_POSN | none | 0x1 |
_LATJ_LATJ1_POSITION | none | 0x1 |
_LATJ_LATJ1_SIZE | none | 0x1 |
_LATJ_LATJ1_LENGTH | none | 0x1 |
_LATJ_LATJ1_MASK | none | 0x2 |
_LATJ_LATJ2_POSN | none | 0x2 |
_LATJ_LATJ2_POSITION | none | 0x2 |
_LATJ_LATJ2_SIZE | none | 0x1 |
_LATJ_LATJ2_LENGTH | none | 0x1 |
_LATJ_LATJ2_MASK | none | 0x4 |
_LATJ_LATJ3_POSN | none | 0x3 |
_LATJ_LATJ3_POSITION | none | 0x3 |
_LATJ_LATJ3_SIZE | none | 0x1 |
_LATJ_LATJ3_LENGTH | none | 0x1 |
_LATJ_LATJ3_MASK | none | 0x8 |
_LATJ_LATJ4_POSN | none | 0x4 |
_LATJ_LATJ4_POSITION | none | 0x4 |
_LATJ_LATJ4_SIZE | none | 0x1 |
_LATJ_LATJ4_LENGTH | none | 0x1 |
_LATJ_LATJ4_MASK | none | 0x10 |
_LATJ_LATJ5_POSN | none | 0x5 |
_LATJ_LATJ5_POSITION | none | 0x5 |
_LATJ_LATJ5_SIZE | none | 0x1 |
_LATJ_LATJ5_LENGTH | none | 0x1 |
_LATJ_LATJ5_MASK | none | 0x20 |
_LATJ_LATJ6_POSN | none | 0x6 |
_LATJ_LATJ6_POSITION | none | 0x6 |
_LATJ_LATJ6_SIZE | none | 0x1 |
_LATJ_LATJ6_LENGTH | none | 0x1 |
_LATJ_LATJ6_MASK | none | 0x40 |
_LATJ_LATJ7_POSN | none | 0x7 |
_LATJ_LATJ7_POSITION | none | 0x7 |
_LATJ_LATJ7_SIZE | none | 0x1 |
_LATJ_LATJ7_LENGTH | none | 0x1 |
_LATJ_LATJ7_MASK | none | 0x80 |
_LATJ_LJ0_POSN | none | 0x0 |
_LATJ_LJ0_POSITION | none | 0x0 |
_LATJ_LJ0_SIZE | none | 0x1 |
_LATJ_LJ0_LENGTH | none | 0x1 |
_LATJ_LJ0_MASK | none | 0x1 |
_LATJ_LJ1_POSN | none | 0x1 |
_LATJ_LJ1_POSITION | none | 0x1 |
_LATJ_LJ1_SIZE | none | 0x1 |
_LATJ_LJ1_LENGTH | none | 0x1 |
_LATJ_LJ1_MASK | none | 0x2 |
_LATJ_LJ2_POSN | none | 0x2 |
_LATJ_LJ2_POSITION | none | 0x2 |
_LATJ_LJ2_SIZE | none | 0x1 |
_LATJ_LJ2_LENGTH | none | 0x1 |
_LATJ_LJ2_MASK | none | 0x4 |
_LATJ_LJ3_POSN | none | 0x3 |
_LATJ_LJ3_POSITION | none | 0x3 |
_LATJ_LJ3_SIZE | none | 0x1 |
_LATJ_LJ3_LENGTH | none | 0x1 |
_LATJ_LJ3_MASK | none | 0x8 |
_LATJ_LJ4_POSN | none | 0x4 |
_LATJ_LJ4_POSITION | none | 0x4 |
_LATJ_LJ4_SIZE | none | 0x1 |
_LATJ_LJ4_LENGTH | none | 0x1 |
_LATJ_LJ4_MASK | none | 0x10 |
_LATJ_LJ5_POSN | none | 0x5 |
_LATJ_LJ5_POSITION | none | 0x5 |
_LATJ_LJ5_SIZE | none | 0x1 |
_LATJ_LJ5_LENGTH | none | 0x1 |
_LATJ_LJ5_MASK | none | 0x20 |
_LATJ_LJ6_POSN | none | 0x6 |
_LATJ_LJ6_POSITION | none | 0x6 |
_LATJ_LJ6_SIZE | none | 0x1 |
_LATJ_LJ6_LENGTH | none | 0x1 |
_LATJ_LJ6_MASK | none | 0x40 |
_LATJ_LJ7_POSN | none | 0x7 |
_LATJ_LJ7_POSITION | none | 0x7 |
_LATJ_LJ7_SIZE | none | 0x1 |
_LATJ_LJ7_LENGTH | none | 0x1 |
_LATJ_LJ7_MASK | none | 0x80 |
TRISA | none | <\077435>TRISA |
TRISA | none | <\077435>TRISA |
_TRISA_TRISA0_POSN | none | 0x0 |
_TRISA_TRISA0_POSITION | none | 0x0 |
_TRISA_TRISA0_SIZE | none | 0x1 |
_TRISA_TRISA0_LENGTH | none | 0x1 |
_TRISA_TRISA0_MASK | none | 0x1 |
_TRISA_TRISA1_POSN | none | 0x1 |
_TRISA_TRISA1_POSITION | none | 0x1 |
_TRISA_TRISA1_SIZE | none | 0x1 |
_TRISA_TRISA1_LENGTH | none | 0x1 |
_TRISA_TRISA1_MASK | none | 0x2 |
_TRISA_TRISA2_POSN | none | 0x2 |
_TRISA_TRISA2_POSITION | none | 0x2 |
_TRISA_TRISA2_SIZE | none | 0x1 |
_TRISA_TRISA2_LENGTH | none | 0x1 |
_TRISA_TRISA2_MASK | none | 0x4 |
_TRISA_TRISA3_POSN | none | 0x3 |
_TRISA_TRISA3_POSITION | none | 0x3 |
_TRISA_TRISA3_SIZE | none | 0x1 |
_TRISA_TRISA3_LENGTH | none | 0x1 |
_TRISA_TRISA3_MASK | none | 0x8 |
_TRISA_TRISA4_POSN | none | 0x4 |
_TRISA_TRISA4_POSITION | none | 0x4 |
_TRISA_TRISA4_SIZE | none | 0x1 |
_TRISA_TRISA4_LENGTH | none | 0x1 |
_TRISA_TRISA4_MASK | none | 0x10 |
_TRISA_TRISA5_POSN | none | 0x5 |
_TRISA_TRISA5_POSITION | none | 0x5 |
_TRISA_TRISA5_SIZE | none | 0x1 |
_TRISA_TRISA5_LENGTH | none | 0x1 |
_TRISA_TRISA5_MASK | none | 0x20 |
_TRISA_TRISA6_POSN | none | 0x6 |
_TRISA_TRISA6_POSITION | none | 0x6 |
_TRISA_TRISA6_SIZE | none | 0x1 |
_TRISA_TRISA6_LENGTH | none | 0x1 |
_TRISA_TRISA6_MASK | none | 0x40 |
_TRISA_RA0_POSN | none | 0x0 |
_TRISA_RA0_POSITION | none | 0x0 |
_TRISA_RA0_SIZE | none | 0x1 |
_TRISA_RA0_LENGTH | none | 0x1 |
_TRISA_RA0_MASK | none | 0x1 |
_TRISA_RA1_POSN | none | 0x1 |
_TRISA_RA1_POSITION | none | 0x1 |
_TRISA_RA1_SIZE | none | 0x1 |
_TRISA_RA1_LENGTH | none | 0x1 |
_TRISA_RA1_MASK | none | 0x2 |
_TRISA_RA2_POSN | none | 0x2 |
_TRISA_RA2_POSITION | none | 0x2 |
_TRISA_RA2_SIZE | none | 0x1 |
_TRISA_RA2_LENGTH | none | 0x1 |
_TRISA_RA2_MASK | none | 0x4 |
_TRISA_RA3_POSN | none | 0x3 |
_TRISA_RA3_POSITION | none | 0x3 |
_TRISA_RA3_SIZE | none | 0x1 |
_TRISA_RA3_LENGTH | none | 0x1 |
_TRISA_RA3_MASK | none | 0x8 |
_TRISA_RA4_POSN | none | 0x4 |
_TRISA_RA4_POSITION | none | 0x4 |
_TRISA_RA4_SIZE | none | 0x1 |
_TRISA_RA4_LENGTH | none | 0x1 |
_TRISA_RA4_MASK | none | 0x10 |
_TRISA_RA5_POSN | none | 0x5 |
_TRISA_RA5_POSITION | none | 0x5 |
_TRISA_RA5_SIZE | none | 0x1 |
_TRISA_RA5_LENGTH | none | 0x1 |
_TRISA_RA5_MASK | none | 0x20 |
_TRISA_RA6_POSN | none | 0x6 |
_TRISA_RA6_POSITION | none | 0x6 |
_TRISA_RA6_SIZE | none | 0x1 |
_TRISA_RA6_LENGTH | none | 0x1 |
_TRISA_RA6_MASK | none | 0x40 |
_DDRA_TRISA0_POSN | none | 0x0 |
_DDRA_TRISA0_POSITION | none | 0x0 |
_DDRA_TRISA0_SIZE | none | 0x1 |
_DDRA_TRISA0_LENGTH | none | 0x1 |
_DDRA_TRISA0_MASK | none | 0x1 |
_DDRA_TRISA1_POSN | none | 0x1 |
_DDRA_TRISA1_POSITION | none | 0x1 |
_DDRA_TRISA1_SIZE | none | 0x1 |
_DDRA_TRISA1_LENGTH | none | 0x1 |
_DDRA_TRISA1_MASK | none | 0x2 |
_DDRA_TRISA2_POSN | none | 0x2 |
_DDRA_TRISA2_POSITION | none | 0x2 |
_DDRA_TRISA2_SIZE | none | 0x1 |
_DDRA_TRISA2_LENGTH | none | 0x1 |
_DDRA_TRISA2_MASK | none | 0x4 |
_DDRA_TRISA3_POSN | none | 0x3 |
_DDRA_TRISA3_POSITION | none | 0x3 |
_DDRA_TRISA3_SIZE | none | 0x1 |
_DDRA_TRISA3_LENGTH | none | 0x1 |
_DDRA_TRISA3_MASK | none | 0x8 |
_DDRA_TRISA4_POSN | none | 0x4 |
_DDRA_TRISA4_POSITION | none | 0x4 |
_DDRA_TRISA4_SIZE | none | 0x1 |
_DDRA_TRISA4_LENGTH | none | 0x1 |
_DDRA_TRISA4_MASK | none | 0x10 |
_DDRA_TRISA5_POSN | none | 0x5 |
_DDRA_TRISA5_POSITION | none | 0x5 |
_DDRA_TRISA5_SIZE | none | 0x1 |
_DDRA_TRISA5_LENGTH | none | 0x1 |
_DDRA_TRISA5_MASK | none | 0x20 |
_DDRA_TRISA6_POSN | none | 0x6 |
_DDRA_TRISA6_POSITION | none | 0x6 |
_DDRA_TRISA6_SIZE | none | 0x1 |
_DDRA_TRISA6_LENGTH | none | 0x1 |
_DDRA_TRISA6_MASK | none | 0x40 |
_DDRA_RA0_POSN | none | 0x0 |
_DDRA_RA0_POSITION | none | 0x0 |
_DDRA_RA0_SIZE | none | 0x1 |
_DDRA_RA0_LENGTH | none | 0x1 |
_DDRA_RA0_MASK | none | 0x1 |
_DDRA_RA1_POSN | none | 0x1 |
_DDRA_RA1_POSITION | none | 0x1 |
_DDRA_RA1_SIZE | none | 0x1 |
_DDRA_RA1_LENGTH | none | 0x1 |
_DDRA_RA1_MASK | none | 0x2 |
_DDRA_RA2_POSN | none | 0x2 |
_DDRA_RA2_POSITION | none | 0x2 |
_DDRA_RA2_SIZE | none | 0x1 |
_DDRA_RA2_LENGTH | none | 0x1 |
_DDRA_RA2_MASK | none | 0x4 |
_DDRA_RA3_POSN | none | 0x3 |
_DDRA_RA3_POSITION | none | 0x3 |
_DDRA_RA3_SIZE | none | 0x1 |
_DDRA_RA3_LENGTH | none | 0x1 |
_DDRA_RA3_MASK | none | 0x8 |
_DDRA_RA4_POSN | none | 0x4 |
_DDRA_RA4_POSITION | none | 0x4 |
_DDRA_RA4_SIZE | none | 0x1 |
_DDRA_RA4_LENGTH | none | 0x1 |
_DDRA_RA4_MASK | none | 0x10 |
_DDRA_RA5_POSN | none | 0x5 |
_DDRA_RA5_POSITION | none | 0x5 |
_DDRA_RA5_SIZE | none | 0x1 |
_DDRA_RA5_LENGTH | none | 0x1 |
_DDRA_RA5_MASK | none | 0x20 |
_DDRA_RA6_POSN | none | 0x6 |
_DDRA_RA6_POSITION | none | 0x6 |
_DDRA_RA6_SIZE | none | 0x1 |
_DDRA_RA6_LENGTH | none | 0x1 |
_DDRA_RA6_MASK | none | 0x40 |
TRISB | none | <\077435>TRISB |
TRISB | none | <\077435>TRISB |
_TRISB_TRISB0_POSN | none | 0x0 |
_TRISB_TRISB0_POSITION | none | 0x0 |
_TRISB_TRISB0_SIZE | none | 0x1 |
_TRISB_TRISB0_LENGTH | none | 0x1 |
_TRISB_TRISB0_MASK | none | 0x1 |
_TRISB_TRISB1_POSN | none | 0x1 |
_TRISB_TRISB1_POSITION | none | 0x1 |
_TRISB_TRISB1_SIZE | none | 0x1 |
_TRISB_TRISB1_LENGTH | none | 0x1 |
_TRISB_TRISB1_MASK | none | 0x2 |
_TRISB_TRISB2_POSN | none | 0x2 |
_TRISB_TRISB2_POSITION | none | 0x2 |
_TRISB_TRISB2_SIZE | none | 0x1 |
_TRISB_TRISB2_LENGTH | none | 0x1 |
_TRISB_TRISB2_MASK | none | 0x4 |
_TRISB_TRISB3_POSN | none | 0x3 |
_TRISB_TRISB3_POSITION | none | 0x3 |
_TRISB_TRISB3_SIZE | none | 0x1 |
_TRISB_TRISB3_LENGTH | none | 0x1 |
_TRISB_TRISB3_MASK | none | 0x8 |
_TRISB_TRISB4_POSN | none | 0x4 |
_TRISB_TRISB4_POSITION | none | 0x4 |
_TRISB_TRISB4_SIZE | none | 0x1 |
_TRISB_TRISB4_LENGTH | none | 0x1 |
_TRISB_TRISB4_MASK | none | 0x10 |
_TRISB_TRISB5_POSN | none | 0x5 |
_TRISB_TRISB5_POSITION | none | 0x5 |
_TRISB_TRISB5_SIZE | none | 0x1 |
_TRISB_TRISB5_LENGTH | none | 0x1 |
_TRISB_TRISB5_MASK | none | 0x20 |
_TRISB_TRISB6_POSN | none | 0x6 |
_TRISB_TRISB6_POSITION | none | 0x6 |
_TRISB_TRISB6_SIZE | none | 0x1 |
_TRISB_TRISB6_LENGTH | none | 0x1 |
_TRISB_TRISB6_MASK | none | 0x40 |
_TRISB_TRISB7_POSN | none | 0x7 |
_TRISB_TRISB7_POSITION | none | 0x7 |
_TRISB_TRISB7_SIZE | none | 0x1 |
_TRISB_TRISB7_LENGTH | none | 0x1 |
_TRISB_TRISB7_MASK | none | 0x80 |
_TRISB_RB0_POSN | none | 0x0 |
_TRISB_RB0_POSITION | none | 0x0 |
_TRISB_RB0_SIZE | none | 0x1 |
_TRISB_RB0_LENGTH | none | 0x1 |
_TRISB_RB0_MASK | none | 0x1 |
_TRISB_RB1_POSN | none | 0x1 |
_TRISB_RB1_POSITION | none | 0x1 |
_TRISB_RB1_SIZE | none | 0x1 |
_TRISB_RB1_LENGTH | none | 0x1 |
_TRISB_RB1_MASK | none | 0x2 |
_TRISB_RB2_POSN | none | 0x2 |
_TRISB_RB2_POSITION | none | 0x2 |
_TRISB_RB2_SIZE | none | 0x1 |
_TRISB_RB2_LENGTH | none | 0x1 |
_TRISB_RB2_MASK | none | 0x4 |
_TRISB_RB3_POSN | none | 0x3 |
_TRISB_RB3_POSITION | none | 0x3 |
_TRISB_RB3_SIZE | none | 0x1 |
_TRISB_RB3_LENGTH | none | 0x1 |
_TRISB_RB3_MASK | none | 0x8 |
_TRISB_RB4_POSN | none | 0x4 |
_TRISB_RB4_POSITION | none | 0x4 |
_TRISB_RB4_SIZE | none | 0x1 |
_TRISB_RB4_LENGTH | none | 0x1 |
_TRISB_RB4_MASK | none | 0x10 |
_TRISB_RB5_POSN | none | 0x5 |
_TRISB_RB5_POSITION | none | 0x5 |
_TRISB_RB5_SIZE | none | 0x1 |
_TRISB_RB5_LENGTH | none | 0x1 |
_TRISB_RB5_MASK | none | 0x20 |
_TRISB_RB6_POSN | none | 0x6 |
_TRISB_RB6_POSITION | none | 0x6 |
_TRISB_RB6_SIZE | none | 0x1 |
_TRISB_RB6_LENGTH | none | 0x1 |
_TRISB_RB6_MASK | none | 0x40 |
_TRISB_RB7_POSN | none | 0x7 |
_TRISB_RB7_POSITION | none | 0x7 |
_TRISB_RB7_SIZE | none | 0x1 |
_TRISB_RB7_LENGTH | none | 0x1 |
_TRISB_RB7_MASK | none | 0x80 |
_DDRB_TRISB0_POSN | none | 0x0 |
_DDRB_TRISB0_POSITION | none | 0x0 |
_DDRB_TRISB0_SIZE | none | 0x1 |
_DDRB_TRISB0_LENGTH | none | 0x1 |
_DDRB_TRISB0_MASK | none | 0x1 |
_DDRB_TRISB1_POSN | none | 0x1 |
_DDRB_TRISB1_POSITION | none | 0x1 |
_DDRB_TRISB1_SIZE | none | 0x1 |
_DDRB_TRISB1_LENGTH | none | 0x1 |
_DDRB_TRISB1_MASK | none | 0x2 |
_DDRB_TRISB2_POSN | none | 0x2 |
_DDRB_TRISB2_POSITION | none | 0x2 |
_DDRB_TRISB2_SIZE | none | 0x1 |
_DDRB_TRISB2_LENGTH | none | 0x1 |
_DDRB_TRISB2_MASK | none | 0x4 |
_DDRB_TRISB3_POSN | none | 0x3 |
_DDRB_TRISB3_POSITION | none | 0x3 |
_DDRB_TRISB3_SIZE | none | 0x1 |
_DDRB_TRISB3_LENGTH | none | 0x1 |
_DDRB_TRISB3_MASK | none | 0x8 |
_DDRB_TRISB4_POSN | none | 0x4 |
_DDRB_TRISB4_POSITION | none | 0x4 |
_DDRB_TRISB4_SIZE | none | 0x1 |
_DDRB_TRISB4_LENGTH | none | 0x1 |
_DDRB_TRISB4_MASK | none | 0x10 |
_DDRB_TRISB5_POSN | none | 0x5 |
_DDRB_TRISB5_POSITION | none | 0x5 |
_DDRB_TRISB5_SIZE | none | 0x1 |
_DDRB_TRISB5_LENGTH | none | 0x1 |
_DDRB_TRISB5_MASK | none | 0x20 |
_DDRB_TRISB6_POSN | none | 0x6 |
_DDRB_TRISB6_POSITION | none | 0x6 |
_DDRB_TRISB6_SIZE | none | 0x1 |
_DDRB_TRISB6_LENGTH | none | 0x1 |
_DDRB_TRISB6_MASK | none | 0x40 |
_DDRB_TRISB7_POSN | none | 0x7 |
_DDRB_TRISB7_POSITION | none | 0x7 |
_DDRB_TRISB7_SIZE | none | 0x1 |
_DDRB_TRISB7_LENGTH | none | 0x1 |
_DDRB_TRISB7_MASK | none | 0x80 |
_DDRB_RB0_POSN | none | 0x0 |
_DDRB_RB0_POSITION | none | 0x0 |
_DDRB_RB0_SIZE | none | 0x1 |
_DDRB_RB0_LENGTH | none | 0x1 |
_DDRB_RB0_MASK | none | 0x1 |
_DDRB_RB1_POSN | none | 0x1 |
_DDRB_RB1_POSITION | none | 0x1 |
_DDRB_RB1_SIZE | none | 0x1 |
_DDRB_RB1_LENGTH | none | 0x1 |
_DDRB_RB1_MASK | none | 0x2 |
_DDRB_RB2_POSN | none | 0x2 |
_DDRB_RB2_POSITION | none | 0x2 |
_DDRB_RB2_SIZE | none | 0x1 |
_DDRB_RB2_LENGTH | none | 0x1 |
_DDRB_RB2_MASK | none | 0x4 |
_DDRB_RB3_POSN | none | 0x3 |
_DDRB_RB3_POSITION | none | 0x3 |
_DDRB_RB3_SIZE | none | 0x1 |
_DDRB_RB3_LENGTH | none | 0x1 |
_DDRB_RB3_MASK | none | 0x8 |
_DDRB_RB4_POSN | none | 0x4 |
_DDRB_RB4_POSITION | none | 0x4 |
_DDRB_RB4_SIZE | none | 0x1 |
_DDRB_RB4_LENGTH | none | 0x1 |
_DDRB_RB4_MASK | none | 0x10 |
_DDRB_RB5_POSN | none | 0x5 |
_DDRB_RB5_POSITION | none | 0x5 |
_DDRB_RB5_SIZE | none | 0x1 |
_DDRB_RB5_LENGTH | none | 0x1 |
_DDRB_RB5_MASK | none | 0x20 |
_DDRB_RB6_POSN | none | 0x6 |
_DDRB_RB6_POSITION | none | 0x6 |
_DDRB_RB6_SIZE | none | 0x1 |
_DDRB_RB6_LENGTH | none | 0x1 |
_DDRB_RB6_MASK | none | 0x40 |
_DDRB_RB7_POSN | none | 0x7 |
_DDRB_RB7_POSITION | none | 0x7 |
_DDRB_RB7_SIZE | none | 0x1 |
_DDRB_RB7_LENGTH | none | 0x1 |
_DDRB_RB7_MASK | none | 0x80 |
TRISC | none | <\077435>TRISC |
TRISC | none | <\077435>TRISC |
_TRISC_TRISC0_POSN | none | 0x0 |
_TRISC_TRISC0_POSITION | none | 0x0 |
_TRISC_TRISC0_SIZE | none | 0x1 |
_TRISC_TRISC0_LENGTH | none | 0x1 |
_TRISC_TRISC0_MASK | none | 0x1 |
_TRISC_TRISC1_POSN | none | 0x1 |
_TRISC_TRISC1_POSITION | none | 0x1 |
_TRISC_TRISC1_SIZE | none | 0x1 |
_TRISC_TRISC1_LENGTH | none | 0x1 |
_TRISC_TRISC1_MASK | none | 0x2 |
_TRISC_TRISC2_POSN | none | 0x2 |
_TRISC_TRISC2_POSITION | none | 0x2 |
_TRISC_TRISC2_SIZE | none | 0x1 |
_TRISC_TRISC2_LENGTH | none | 0x1 |
_TRISC_TRISC2_MASK | none | 0x4 |
_TRISC_TRISC3_POSN | none | 0x3 |
_TRISC_TRISC3_POSITION | none | 0x3 |
_TRISC_TRISC3_SIZE | none | 0x1 |
_TRISC_TRISC3_LENGTH | none | 0x1 |
_TRISC_TRISC3_MASK | none | 0x8 |
_TRISC_TRISC4_POSN | none | 0x4 |
_TRISC_TRISC4_POSITION | none | 0x4 |
_TRISC_TRISC4_SIZE | none | 0x1 |
_TRISC_TRISC4_LENGTH | none | 0x1 |
_TRISC_TRISC4_MASK | none | 0x10 |
_TRISC_TRISC5_POSN | none | 0x5 |
_TRISC_TRISC5_POSITION | none | 0x5 |
_TRISC_TRISC5_SIZE | none | 0x1 |
_TRISC_TRISC5_LENGTH | none | 0x1 |
_TRISC_TRISC5_MASK | none | 0x20 |
_TRISC_TRISC6_POSN | none | 0x6 |
_TRISC_TRISC6_POSITION | none | 0x6 |
_TRISC_TRISC6_SIZE | none | 0x1 |
_TRISC_TRISC6_LENGTH | none | 0x1 |
_TRISC_TRISC6_MASK | none | 0x40 |
_TRISC_TRISC7_POSN | none | 0x7 |
_TRISC_TRISC7_POSITION | none | 0x7 |
_TRISC_TRISC7_SIZE | none | 0x1 |
_TRISC_TRISC7_LENGTH | none | 0x1 |
_TRISC_TRISC7_MASK | none | 0x80 |
_TRISC_RC0_POSN | none | 0x0 |
_TRISC_RC0_POSITION | none | 0x0 |
_TRISC_RC0_SIZE | none | 0x1 |
_TRISC_RC0_LENGTH | none | 0x1 |
_TRISC_RC0_MASK | none | 0x1 |
_TRISC_RC1_POSN | none | 0x1 |
_TRISC_RC1_POSITION | none | 0x1 |
_TRISC_RC1_SIZE | none | 0x1 |
_TRISC_RC1_LENGTH | none | 0x1 |
_TRISC_RC1_MASK | none | 0x2 |
_TRISC_RC2_POSN | none | 0x2 |
_TRISC_RC2_POSITION | none | 0x2 |
_TRISC_RC2_SIZE | none | 0x1 |
_TRISC_RC2_LENGTH | none | 0x1 |
_TRISC_RC2_MASK | none | 0x4 |
_TRISC_RC3_POSN | none | 0x3 |
_TRISC_RC3_POSITION | none | 0x3 |
_TRISC_RC3_SIZE | none | 0x1 |
_TRISC_RC3_LENGTH | none | 0x1 |
_TRISC_RC3_MASK | none | 0x8 |
_TRISC_RC4_POSN | none | 0x4 |
_TRISC_RC4_POSITION | none | 0x4 |
_TRISC_RC4_SIZE | none | 0x1 |
_TRISC_RC4_LENGTH | none | 0x1 |
_TRISC_RC4_MASK | none | 0x10 |
_TRISC_RC5_POSN | none | 0x5 |
_TRISC_RC5_POSITION | none | 0x5 |
_TRISC_RC5_SIZE | none | 0x1 |
_TRISC_RC5_LENGTH | none | 0x1 |
_TRISC_RC5_MASK | none | 0x20 |
_TRISC_RC6_POSN | none | 0x6 |
_TRISC_RC6_POSITION | none | 0x6 |
_TRISC_RC6_SIZE | none | 0x1 |
_TRISC_RC6_LENGTH | none | 0x1 |
_TRISC_RC6_MASK | none | 0x40 |
_TRISC_RC7_POSN | none | 0x7 |
_TRISC_RC7_POSITION | none | 0x7 |
_TRISC_RC7_SIZE | none | 0x1 |
_TRISC_RC7_LENGTH | none | 0x1 |
_TRISC_RC7_MASK | none | 0x80 |
_DDRC_TRISC0_POSN | none | 0x0 |
_DDRC_TRISC0_POSITION | none | 0x0 |
_DDRC_TRISC0_SIZE | none | 0x1 |
_DDRC_TRISC0_LENGTH | none | 0x1 |
_DDRC_TRISC0_MASK | none | 0x1 |
_DDRC_TRISC1_POSN | none | 0x1 |
_DDRC_TRISC1_POSITION | none | 0x1 |
_DDRC_TRISC1_SIZE | none | 0x1 |
_DDRC_TRISC1_LENGTH | none | 0x1 |
_DDRC_TRISC1_MASK | none | 0x2 |
_DDRC_TRISC2_POSN | none | 0x2 |
_DDRC_TRISC2_POSITION | none | 0x2 |
_DDRC_TRISC2_SIZE | none | 0x1 |
_DDRC_TRISC2_LENGTH | none | 0x1 |
_DDRC_TRISC2_MASK | none | 0x4 |
_DDRC_TRISC3_POSN | none | 0x3 |
_DDRC_TRISC3_POSITION | none | 0x3 |
_DDRC_TRISC3_SIZE | none | 0x1 |
_DDRC_TRISC3_LENGTH | none | 0x1 |
_DDRC_TRISC3_MASK | none | 0x8 |
_DDRC_TRISC4_POSN | none | 0x4 |
_DDRC_TRISC4_POSITION | none | 0x4 |
_DDRC_TRISC4_SIZE | none | 0x1 |
_DDRC_TRISC4_LENGTH | none | 0x1 |
_DDRC_TRISC4_MASK | none | 0x10 |
_DDRC_TRISC5_POSN | none | 0x5 |
_DDRC_TRISC5_POSITION | none | 0x5 |
_DDRC_TRISC5_SIZE | none | 0x1 |
_DDRC_TRISC5_LENGTH | none | 0x1 |
_DDRC_TRISC5_MASK | none | 0x20 |
_DDRC_TRISC6_POSN | none | 0x6 |
_DDRC_TRISC6_POSITION | none | 0x6 |
_DDRC_TRISC6_SIZE | none | 0x1 |
_DDRC_TRISC6_LENGTH | none | 0x1 |
_DDRC_TRISC6_MASK | none | 0x40 |
_DDRC_TRISC7_POSN | none | 0x7 |
_DDRC_TRISC7_POSITION | none | 0x7 |
_DDRC_TRISC7_SIZE | none | 0x1 |
_DDRC_TRISC7_LENGTH | none | 0x1 |
_DDRC_TRISC7_MASK | none | 0x80 |
_DDRC_RC0_POSN | none | 0x0 |
_DDRC_RC0_POSITION | none | 0x0 |
_DDRC_RC0_SIZE | none | 0x1 |
_DDRC_RC0_LENGTH | none | 0x1 |
_DDRC_RC0_MASK | none | 0x1 |
_DDRC_RC1_POSN | none | 0x1 |
_DDRC_RC1_POSITION | none | 0x1 |
_DDRC_RC1_SIZE | none | 0x1 |
_DDRC_RC1_LENGTH | none | 0x1 |
_DDRC_RC1_MASK | none | 0x2 |
_DDRC_RC2_POSN | none | 0x2 |
_DDRC_RC2_POSITION | none | 0x2 |
_DDRC_RC2_SIZE | none | 0x1 |
_DDRC_RC2_LENGTH | none | 0x1 |
_DDRC_RC2_MASK | none | 0x4 |
_DDRC_RC3_POSN | none | 0x3 |
_DDRC_RC3_POSITION | none | 0x3 |
_DDRC_RC3_SIZE | none | 0x1 |
_DDRC_RC3_LENGTH | none | 0x1 |
_DDRC_RC3_MASK | none | 0x8 |
_DDRC_RC4_POSN | none | 0x4 |
_DDRC_RC4_POSITION | none | 0x4 |
_DDRC_RC4_SIZE | none | 0x1 |
_DDRC_RC4_LENGTH | none | 0x1 |
_DDRC_RC4_MASK | none | 0x10 |
_DDRC_RC5_POSN | none | 0x5 |
_DDRC_RC5_POSITION | none | 0x5 |
_DDRC_RC5_SIZE | none | 0x1 |
_DDRC_RC5_LENGTH | none | 0x1 |
_DDRC_RC5_MASK | none | 0x20 |
_DDRC_RC6_POSN | none | 0x6 |
_DDRC_RC6_POSITION | none | 0x6 |
_DDRC_RC6_SIZE | none | 0x1 |
_DDRC_RC6_LENGTH | none | 0x1 |
_DDRC_RC6_MASK | none | 0x40 |
_DDRC_RC7_POSN | none | 0x7 |
_DDRC_RC7_POSITION | none | 0x7 |
_DDRC_RC7_SIZE | none | 0x1 |
_DDRC_RC7_LENGTH | none | 0x1 |
_DDRC_RC7_MASK | none | 0x80 |
TRISD | none | <\077435>TRISD |
TRISD | none | <\077435>TRISD |
_TRISD_TRISD0_POSN | none | 0x0 |
_TRISD_TRISD0_POSITION | none | 0x0 |
_TRISD_TRISD0_SIZE | none | 0x1 |
_TRISD_TRISD0_LENGTH | none | 0x1 |
_TRISD_TRISD0_MASK | none | 0x1 |
_TRISD_TRISD1_POSN | none | 0x1 |
_TRISD_TRISD1_POSITION | none | 0x1 |
_TRISD_TRISD1_SIZE | none | 0x1 |
_TRISD_TRISD1_LENGTH | none | 0x1 |
_TRISD_TRISD1_MASK | none | 0x2 |
_TRISD_TRISD2_POSN | none | 0x2 |
_TRISD_TRISD2_POSITION | none | 0x2 |
_TRISD_TRISD2_SIZE | none | 0x1 |
_TRISD_TRISD2_LENGTH | none | 0x1 |
_TRISD_TRISD2_MASK | none | 0x4 |
_TRISD_TRISD3_POSN | none | 0x3 |
_TRISD_TRISD3_POSITION | none | 0x3 |
_TRISD_TRISD3_SIZE | none | 0x1 |
_TRISD_TRISD3_LENGTH | none | 0x1 |
_TRISD_TRISD3_MASK | none | 0x8 |
_TRISD_TRISD4_POSN | none | 0x4 |
_TRISD_TRISD4_POSITION | none | 0x4 |
_TRISD_TRISD4_SIZE | none | 0x1 |
_TRISD_TRISD4_LENGTH | none | 0x1 |
_TRISD_TRISD4_MASK | none | 0x10 |
_TRISD_TRISD5_POSN | none | 0x5 |
_TRISD_TRISD5_POSITION | none | 0x5 |
_TRISD_TRISD5_SIZE | none | 0x1 |
_TRISD_TRISD5_LENGTH | none | 0x1 |
_TRISD_TRISD5_MASK | none | 0x20 |
_TRISD_TRISD6_POSN | none | 0x6 |
_TRISD_TRISD6_POSITION | none | 0x6 |
_TRISD_TRISD6_SIZE | none | 0x1 |
_TRISD_TRISD6_LENGTH | none | 0x1 |
_TRISD_TRISD6_MASK | none | 0x40 |
_TRISD_TRISD7_POSN | none | 0x7 |
_TRISD_TRISD7_POSITION | none | 0x7 |
_TRISD_TRISD7_SIZE | none | 0x1 |
_TRISD_TRISD7_LENGTH | none | 0x1 |
_TRISD_TRISD7_MASK | none | 0x80 |
_TRISD_RD0_POSN | none | 0x0 |
_TRISD_RD0_POSITION | none | 0x0 |
_TRISD_RD0_SIZE | none | 0x1 |
_TRISD_RD0_LENGTH | none | 0x1 |
_TRISD_RD0_MASK | none | 0x1 |
_TRISD_RD1_POSN | none | 0x1 |
_TRISD_RD1_POSITION | none | 0x1 |
_TRISD_RD1_SIZE | none | 0x1 |
_TRISD_RD1_LENGTH | none | 0x1 |
_TRISD_RD1_MASK | none | 0x2 |
_TRISD_RD2_POSN | none | 0x2 |
_TRISD_RD2_POSITION | none | 0x2 |
_TRISD_RD2_SIZE | none | 0x1 |
_TRISD_RD2_LENGTH | none | 0x1 |
_TRISD_RD2_MASK | none | 0x4 |
_TRISD_RD3_POSN | none | 0x3 |
_TRISD_RD3_POSITION | none | 0x3 |
_TRISD_RD3_SIZE | none | 0x1 |
_TRISD_RD3_LENGTH | none | 0x1 |
_TRISD_RD3_MASK | none | 0x8 |
_TRISD_RD4_POSN | none | 0x4 |
_TRISD_RD4_POSITION | none | 0x4 |
_TRISD_RD4_SIZE | none | 0x1 |
_TRISD_RD4_LENGTH | none | 0x1 |
_TRISD_RD4_MASK | none | 0x10 |
_TRISD_RD5_POSN | none | 0x5 |
_TRISD_RD5_POSITION | none | 0x5 |
_TRISD_RD5_SIZE | none | 0x1 |
_TRISD_RD5_LENGTH | none | 0x1 |
_TRISD_RD5_MASK | none | 0x20 |
_TRISD_RD6_POSN | none | 0x6 |
_TRISD_RD6_POSITION | none | 0x6 |
_TRISD_RD6_SIZE | none | 0x1 |
_TRISD_RD6_LENGTH | none | 0x1 |
_TRISD_RD6_MASK | none | 0x40 |
_TRISD_RD7_POSN | none | 0x7 |
_TRISD_RD7_POSITION | none | 0x7 |
_TRISD_RD7_SIZE | none | 0x1 |
_TRISD_RD7_LENGTH | none | 0x1 |
_TRISD_RD7_MASK | none | 0x80 |
_DDRD_TRISD0_POSN | none | 0x0 |
_DDRD_TRISD0_POSITION | none | 0x0 |
_DDRD_TRISD0_SIZE | none | 0x1 |
_DDRD_TRISD0_LENGTH | none | 0x1 |
_DDRD_TRISD0_MASK | none | 0x1 |
_DDRD_TRISD1_POSN | none | 0x1 |
_DDRD_TRISD1_POSITION | none | 0x1 |
_DDRD_TRISD1_SIZE | none | 0x1 |
_DDRD_TRISD1_LENGTH | none | 0x1 |
_DDRD_TRISD1_MASK | none | 0x2 |
_DDRD_TRISD2_POSN | none | 0x2 |
_DDRD_TRISD2_POSITION | none | 0x2 |
_DDRD_TRISD2_SIZE | none | 0x1 |
_DDRD_TRISD2_LENGTH | none | 0x1 |
_DDRD_TRISD2_MASK | none | 0x4 |
_DDRD_TRISD3_POSN | none | 0x3 |
_DDRD_TRISD3_POSITION | none | 0x3 |
_DDRD_TRISD3_SIZE | none | 0x1 |
_DDRD_TRISD3_LENGTH | none | 0x1 |
_DDRD_TRISD3_MASK | none | 0x8 |
_DDRD_TRISD4_POSN | none | 0x4 |
_DDRD_TRISD4_POSITION | none | 0x4 |
_DDRD_TRISD4_SIZE | none | 0x1 |
_DDRD_TRISD4_LENGTH | none | 0x1 |
_DDRD_TRISD4_MASK | none | 0x10 |
_DDRD_TRISD5_POSN | none | 0x5 |
_DDRD_TRISD5_POSITION | none | 0x5 |
_DDRD_TRISD5_SIZE | none | 0x1 |
_DDRD_TRISD5_LENGTH | none | 0x1 |
_DDRD_TRISD5_MASK | none | 0x20 |
_DDRD_TRISD6_POSN | none | 0x6 |
_DDRD_TRISD6_POSITION | none | 0x6 |
_DDRD_TRISD6_SIZE | none | 0x1 |
_DDRD_TRISD6_LENGTH | none | 0x1 |
_DDRD_TRISD6_MASK | none | 0x40 |
_DDRD_TRISD7_POSN | none | 0x7 |
_DDRD_TRISD7_POSITION | none | 0x7 |
_DDRD_TRISD7_SIZE | none | 0x1 |
_DDRD_TRISD7_LENGTH | none | 0x1 |
_DDRD_TRISD7_MASK | none | 0x80 |
_DDRD_RD0_POSN | none | 0x0 |
_DDRD_RD0_POSITION | none | 0x0 |
_DDRD_RD0_SIZE | none | 0x1 |
_DDRD_RD0_LENGTH | none | 0x1 |
_DDRD_RD0_MASK | none | 0x1 |
_DDRD_RD1_POSN | none | 0x1 |
_DDRD_RD1_POSITION | none | 0x1 |
_DDRD_RD1_SIZE | none | 0x1 |
_DDRD_RD1_LENGTH | none | 0x1 |
_DDRD_RD1_MASK | none | 0x2 |
_DDRD_RD2_POSN | none | 0x2 |
_DDRD_RD2_POSITION | none | 0x2 |
_DDRD_RD2_SIZE | none | 0x1 |
_DDRD_RD2_LENGTH | none | 0x1 |
_DDRD_RD2_MASK | none | 0x4 |
_DDRD_RD3_POSN | none | 0x3 |
_DDRD_RD3_POSITION | none | 0x3 |
_DDRD_RD3_SIZE | none | 0x1 |
_DDRD_RD3_LENGTH | none | 0x1 |
_DDRD_RD3_MASK | none | 0x8 |
_DDRD_RD4_POSN | none | 0x4 |
_DDRD_RD4_POSITION | none | 0x4 |
_DDRD_RD4_SIZE | none | 0x1 |
_DDRD_RD4_LENGTH | none | 0x1 |
_DDRD_RD4_MASK | none | 0x10 |
_DDRD_RD5_POSN | none | 0x5 |
_DDRD_RD5_POSITION | none | 0x5 |
_DDRD_RD5_SIZE | none | 0x1 |
_DDRD_RD5_LENGTH | none | 0x1 |
_DDRD_RD5_MASK | none | 0x20 |
_DDRD_RD6_POSN | none | 0x6 |
_DDRD_RD6_POSITION | none | 0x6 |
_DDRD_RD6_SIZE | none | 0x1 |
_DDRD_RD6_LENGTH | none | 0x1 |
_DDRD_RD6_MASK | none | 0x40 |
_DDRD_RD7_POSN | none | 0x7 |
_DDRD_RD7_POSITION | none | 0x7 |
_DDRD_RD7_SIZE | none | 0x1 |
_DDRD_RD7_LENGTH | none | 0x1 |
_DDRD_RD7_MASK | none | 0x80 |
TRISE | none | <\077435>TRISE |
TRISE | none | <\077435>TRISE |
_TRISE_TRISE0_POSN | none | 0x0 |
_TRISE_TRISE0_POSITION | none | 0x0 |
_TRISE_TRISE0_SIZE | none | 0x1 |
_TRISE_TRISE0_LENGTH | none | 0x1 |
_TRISE_TRISE0_MASK | none | 0x1 |
_TRISE_TRISE1_POSN | none | 0x1 |
_TRISE_TRISE1_POSITION | none | 0x1 |
_TRISE_TRISE1_SIZE | none | 0x1 |
_TRISE_TRISE1_LENGTH | none | 0x1 |
_TRISE_TRISE1_MASK | none | 0x2 |
_TRISE_TRISE2_POSN | none | 0x2 |
_TRISE_TRISE2_POSITION | none | 0x2 |
_TRISE_TRISE2_SIZE | none | 0x1 |
_TRISE_TRISE2_LENGTH | none | 0x1 |
_TRISE_TRISE2_MASK | none | 0x4 |
_TRISE_TRISE3_POSN | none | 0x3 |
_TRISE_TRISE3_POSITION | none | 0x3 |
_TRISE_TRISE3_SIZE | none | 0x1 |
_TRISE_TRISE3_LENGTH | none | 0x1 |
_TRISE_TRISE3_MASK | none | 0x8 |
_TRISE_TRISE4_POSN | none | 0x4 |
_TRISE_TRISE4_POSITION | none | 0x4 |
_TRISE_TRISE4_SIZE | none | 0x1 |
_TRISE_TRISE4_LENGTH | none | 0x1 |
_TRISE_TRISE4_MASK | none | 0x10 |
_TRISE_TRISE5_POSN | none | 0x5 |
_TRISE_TRISE5_POSITION | none | 0x5 |
_TRISE_TRISE5_SIZE | none | 0x1 |
_TRISE_TRISE5_LENGTH | none | 0x1 |
_TRISE_TRISE5_MASK | none | 0x20 |
_TRISE_TRISE6_POSN | none | 0x6 |
_TRISE_TRISE6_POSITION | none | 0x6 |
_TRISE_TRISE6_SIZE | none | 0x1 |
_TRISE_TRISE6_LENGTH | none | 0x1 |
_TRISE_TRISE6_MASK | none | 0x40 |
_TRISE_TRISE7_POSN | none | 0x7 |
_TRISE_TRISE7_POSITION | none | 0x7 |
_TRISE_TRISE7_SIZE | none | 0x1 |
_TRISE_TRISE7_LENGTH | none | 0x1 |
_TRISE_TRISE7_MASK | none | 0x80 |
_TRISE_RE0_POSN | none | 0x0 |
_TRISE_RE0_POSITION | none | 0x0 |
_TRISE_RE0_SIZE | none | 0x1 |
_TRISE_RE0_LENGTH | none | 0x1 |
_TRISE_RE0_MASK | none | 0x1 |
_TRISE_RE1_POSN | none | 0x1 |
_TRISE_RE1_POSITION | none | 0x1 |
_TRISE_RE1_SIZE | none | 0x1 |
_TRISE_RE1_LENGTH | none | 0x1 |
_TRISE_RE1_MASK | none | 0x2 |
_TRISE_RE2_POSN | none | 0x2 |
_TRISE_RE2_POSITION | none | 0x2 |
_TRISE_RE2_SIZE | none | 0x1 |
_TRISE_RE2_LENGTH | none | 0x1 |
_TRISE_RE2_MASK | none | 0x4 |
_TRISE_RE3_POSN | none | 0x3 |
_TRISE_RE3_POSITION | none | 0x3 |
_TRISE_RE3_SIZE | none | 0x1 |
_TRISE_RE3_LENGTH | none | 0x1 |
_TRISE_RE3_MASK | none | 0x8 |
_TRISE_RE4_POSN | none | 0x4 |
_TRISE_RE4_POSITION | none | 0x4 |
_TRISE_RE4_SIZE | none | 0x1 |
_TRISE_RE4_LENGTH | none | 0x1 |
_TRISE_RE4_MASK | none | 0x10 |
_TRISE_RE5_POSN | none | 0x5 |
_TRISE_RE5_POSITION | none | 0x5 |
_TRISE_RE5_SIZE | none | 0x1 |
_TRISE_RE5_LENGTH | none | 0x1 |
_TRISE_RE5_MASK | none | 0x20 |
_TRISE_RE6_POSN | none | 0x6 |
_TRISE_RE6_POSITION | none | 0x6 |
_TRISE_RE6_SIZE | none | 0x1 |
_TRISE_RE6_LENGTH | none | 0x1 |
_TRISE_RE6_MASK | none | 0x40 |
_TRISE_RE7_POSN | none | 0x7 |
_TRISE_RE7_POSITION | none | 0x7 |
_TRISE_RE7_SIZE | none | 0x1 |
_TRISE_RE7_LENGTH | none | 0x1 |
_TRISE_RE7_MASK | none | 0x80 |
_DDRE_TRISE0_POSN | none | 0x0 |
_DDRE_TRISE0_POSITION | none | 0x0 |
_DDRE_TRISE0_SIZE | none | 0x1 |
_DDRE_TRISE0_LENGTH | none | 0x1 |
_DDRE_TRISE0_MASK | none | 0x1 |
_DDRE_TRISE1_POSN | none | 0x1 |
_DDRE_TRISE1_POSITION | none | 0x1 |
_DDRE_TRISE1_SIZE | none | 0x1 |
_DDRE_TRISE1_LENGTH | none | 0x1 |
_DDRE_TRISE1_MASK | none | 0x2 |
_DDRE_TRISE2_POSN | none | 0x2 |
_DDRE_TRISE2_POSITION | none | 0x2 |
_DDRE_TRISE2_SIZE | none | 0x1 |
_DDRE_TRISE2_LENGTH | none | 0x1 |
_DDRE_TRISE2_MASK | none | 0x4 |
_DDRE_TRISE3_POSN | none | 0x3 |
_DDRE_TRISE3_POSITION | none | 0x3 |
_DDRE_TRISE3_SIZE | none | 0x1 |
_DDRE_TRISE3_LENGTH | none | 0x1 |
_DDRE_TRISE3_MASK | none | 0x8 |
_DDRE_TRISE4_POSN | none | 0x4 |
_DDRE_TRISE4_POSITION | none | 0x4 |
_DDRE_TRISE4_SIZE | none | 0x1 |
_DDRE_TRISE4_LENGTH | none | 0x1 |
_DDRE_TRISE4_MASK | none | 0x10 |
_DDRE_TRISE5_POSN | none | 0x5 |
_DDRE_TRISE5_POSITION | none | 0x5 |
_DDRE_TRISE5_SIZE | none | 0x1 |
_DDRE_TRISE5_LENGTH | none | 0x1 |
_DDRE_TRISE5_MASK | none | 0x20 |
_DDRE_TRISE6_POSN | none | 0x6 |
_DDRE_TRISE6_POSITION | none | 0x6 |
_DDRE_TRISE6_SIZE | none | 0x1 |
_DDRE_TRISE6_LENGTH | none | 0x1 |
_DDRE_TRISE6_MASK | none | 0x40 |
_DDRE_TRISE7_POSN | none | 0x7 |
_DDRE_TRISE7_POSITION | none | 0x7 |
_DDRE_TRISE7_SIZE | none | 0x1 |
_DDRE_TRISE7_LENGTH | none | 0x1 |
_DDRE_TRISE7_MASK | none | 0x80 |
_DDRE_RE0_POSN | none | 0x0 |
_DDRE_RE0_POSITION | none | 0x0 |
_DDRE_RE0_SIZE | none | 0x1 |
_DDRE_RE0_LENGTH | none | 0x1 |
_DDRE_RE0_MASK | none | 0x1 |
_DDRE_RE1_POSN | none | 0x1 |
_DDRE_RE1_POSITION | none | 0x1 |
_DDRE_RE1_SIZE | none | 0x1 |
_DDRE_RE1_LENGTH | none | 0x1 |
_DDRE_RE1_MASK | none | 0x2 |
_DDRE_RE2_POSN | none | 0x2 |
_DDRE_RE2_POSITION | none | 0x2 |
_DDRE_RE2_SIZE | none | 0x1 |
_DDRE_RE2_LENGTH | none | 0x1 |
_DDRE_RE2_MASK | none | 0x4 |
_DDRE_RE3_POSN | none | 0x3 |
_DDRE_RE3_POSITION | none | 0x3 |
_DDRE_RE3_SIZE | none | 0x1 |
_DDRE_RE3_LENGTH | none | 0x1 |
_DDRE_RE3_MASK | none | 0x8 |
_DDRE_RE4_POSN | none | 0x4 |
_DDRE_RE4_POSITION | none | 0x4 |
_DDRE_RE4_SIZE | none | 0x1 |
_DDRE_RE4_LENGTH | none | 0x1 |
_DDRE_RE4_MASK | none | 0x10 |
_DDRE_RE5_POSN | none | 0x5 |
_DDRE_RE5_POSITION | none | 0x5 |
_DDRE_RE5_SIZE | none | 0x1 |
_DDRE_RE5_LENGTH | none | 0x1 |
_DDRE_RE5_MASK | none | 0x20 |
_DDRE_RE6_POSN | none | 0x6 |
_DDRE_RE6_POSITION | none | 0x6 |
_DDRE_RE6_SIZE | none | 0x1 |
_DDRE_RE6_LENGTH | none | 0x1 |
_DDRE_RE6_MASK | none | 0x40 |
_DDRE_RE7_POSN | none | 0x7 |
_DDRE_RE7_POSITION | none | 0x7 |
_DDRE_RE7_SIZE | none | 0x1 |
_DDRE_RE7_LENGTH | none | 0x1 |
_DDRE_RE7_MASK | none | 0x80 |
TRISF | none | <\077435>TRISF |
TRISF | none | <\077435>TRISF |
_TRISF_TRISF0_POSN | none | 0x0 |
_TRISF_TRISF0_POSITION | none | 0x0 |
_TRISF_TRISF0_SIZE | none | 0x1 |
_TRISF_TRISF0_LENGTH | none | 0x1 |
_TRISF_TRISF0_MASK | none | 0x1 |
_TRISF_TRISF1_POSN | none | 0x1 |
_TRISF_TRISF1_POSITION | none | 0x1 |
_TRISF_TRISF1_SIZE | none | 0x1 |
_TRISF_TRISF1_LENGTH | none | 0x1 |
_TRISF_TRISF1_MASK | none | 0x2 |
_TRISF_TRISF2_POSN | none | 0x2 |
_TRISF_TRISF2_POSITION | none | 0x2 |
_TRISF_TRISF2_SIZE | none | 0x1 |
_TRISF_TRISF2_LENGTH | none | 0x1 |
_TRISF_TRISF2_MASK | none | 0x4 |
_TRISF_TRISF3_POSN | none | 0x3 |
_TRISF_TRISF3_POSITION | none | 0x3 |
_TRISF_TRISF3_SIZE | none | 0x1 |
_TRISF_TRISF3_LENGTH | none | 0x1 |
_TRISF_TRISF3_MASK | none | 0x8 |
_TRISF_TRISF4_POSN | none | 0x4 |
_TRISF_TRISF4_POSITION | none | 0x4 |
_TRISF_TRISF4_SIZE | none | 0x1 |
_TRISF_TRISF4_LENGTH | none | 0x1 |
_TRISF_TRISF4_MASK | none | 0x10 |
_TRISF_TRISF5_POSN | none | 0x5 |
_TRISF_TRISF5_POSITION | none | 0x5 |
_TRISF_TRISF5_SIZE | none | 0x1 |
_TRISF_TRISF5_LENGTH | none | 0x1 |
_TRISF_TRISF5_MASK | none | 0x20 |
_TRISF_TRISF6_POSN | none | 0x6 |
_TRISF_TRISF6_POSITION | none | 0x6 |
_TRISF_TRISF6_SIZE | none | 0x1 |
_TRISF_TRISF6_LENGTH | none | 0x1 |
_TRISF_TRISF6_MASK | none | 0x40 |
_TRISF_TRISF7_POSN | none | 0x7 |
_TRISF_TRISF7_POSITION | none | 0x7 |
_TRISF_TRISF7_SIZE | none | 0x1 |
_TRISF_TRISF7_LENGTH | none | 0x1 |
_TRISF_TRISF7_MASK | none | 0x80 |
_TRISF_RF0_POSN | none | 0x0 |
_TRISF_RF0_POSITION | none | 0x0 |
_TRISF_RF0_SIZE | none | 0x1 |
_TRISF_RF0_LENGTH | none | 0x1 |
_TRISF_RF0_MASK | none | 0x1 |
_TRISF_RF1_POSN | none | 0x1 |
_TRISF_RF1_POSITION | none | 0x1 |
_TRISF_RF1_SIZE | none | 0x1 |
_TRISF_RF1_LENGTH | none | 0x1 |
_TRISF_RF1_MASK | none | 0x2 |
_TRISF_RF2_POSN | none | 0x2 |
_TRISF_RF2_POSITION | none | 0x2 |
_TRISF_RF2_SIZE | none | 0x1 |
_TRISF_RF2_LENGTH | none | 0x1 |
_TRISF_RF2_MASK | none | 0x4 |
_TRISF_RF3_POSN | none | 0x3 |
_TRISF_RF3_POSITION | none | 0x3 |
_TRISF_RF3_SIZE | none | 0x1 |
_TRISF_RF3_LENGTH | none | 0x1 |
_TRISF_RF3_MASK | none | 0x8 |
_TRISF_RF4_POSN | none | 0x4 |
_TRISF_RF4_POSITION | none | 0x4 |
_TRISF_RF4_SIZE | none | 0x1 |
_TRISF_RF4_LENGTH | none | 0x1 |
_TRISF_RF4_MASK | none | 0x10 |
_TRISF_RF5_POSN | none | 0x5 |
_TRISF_RF5_POSITION | none | 0x5 |
_TRISF_RF5_SIZE | none | 0x1 |
_TRISF_RF5_LENGTH | none | 0x1 |
_TRISF_RF5_MASK | none | 0x20 |
_TRISF_RF6_POSN | none | 0x6 |
_TRISF_RF6_POSITION | none | 0x6 |
_TRISF_RF6_SIZE | none | 0x1 |
_TRISF_RF6_LENGTH | none | 0x1 |
_TRISF_RF6_MASK | none | 0x40 |
_TRISF_RF7_POSN | none | 0x7 |
_TRISF_RF7_POSITION | none | 0x7 |
_TRISF_RF7_SIZE | none | 0x1 |
_TRISF_RF7_LENGTH | none | 0x1 |
_TRISF_RF7_MASK | none | 0x80 |
_DDRF_TRISF0_POSN | none | 0x0 |
_DDRF_TRISF0_POSITION | none | 0x0 |
_DDRF_TRISF0_SIZE | none | 0x1 |
_DDRF_TRISF0_LENGTH | none | 0x1 |
_DDRF_TRISF0_MASK | none | 0x1 |
_DDRF_TRISF1_POSN | none | 0x1 |
_DDRF_TRISF1_POSITION | none | 0x1 |
_DDRF_TRISF1_SIZE | none | 0x1 |
_DDRF_TRISF1_LENGTH | none | 0x1 |
_DDRF_TRISF1_MASK | none | 0x2 |
_DDRF_TRISF2_POSN | none | 0x2 |
_DDRF_TRISF2_POSITION | none | 0x2 |
_DDRF_TRISF2_SIZE | none | 0x1 |
_DDRF_TRISF2_LENGTH | none | 0x1 |
_DDRF_TRISF2_MASK | none | 0x4 |
_DDRF_TRISF3_POSN | none | 0x3 |
_DDRF_TRISF3_POSITION | none | 0x3 |
_DDRF_TRISF3_SIZE | none | 0x1 |
_DDRF_TRISF3_LENGTH | none | 0x1 |
_DDRF_TRISF3_MASK | none | 0x8 |
_DDRF_TRISF4_POSN | none | 0x4 |
_DDRF_TRISF4_POSITION | none | 0x4 |
_DDRF_TRISF4_SIZE | none | 0x1 |
_DDRF_TRISF4_LENGTH | none | 0x1 |
_DDRF_TRISF4_MASK | none | 0x10 |
_DDRF_TRISF5_POSN | none | 0x5 |
_DDRF_TRISF5_POSITION | none | 0x5 |
_DDRF_TRISF5_SIZE | none | 0x1 |
_DDRF_TRISF5_LENGTH | none | 0x1 |
_DDRF_TRISF5_MASK | none | 0x20 |
_DDRF_TRISF6_POSN | none | 0x6 |
_DDRF_TRISF6_POSITION | none | 0x6 |
_DDRF_TRISF6_SIZE | none | 0x1 |
_DDRF_TRISF6_LENGTH | none | 0x1 |
_DDRF_TRISF6_MASK | none | 0x40 |
_DDRF_TRISF7_POSN | none | 0x7 |
_DDRF_TRISF7_POSITION | none | 0x7 |
_DDRF_TRISF7_SIZE | none | 0x1 |
_DDRF_TRISF7_LENGTH | none | 0x1 |
_DDRF_TRISF7_MASK | none | 0x80 |
_DDRF_RF0_POSN | none | 0x0 |
_DDRF_RF0_POSITION | none | 0x0 |
_DDRF_RF0_SIZE | none | 0x1 |
_DDRF_RF0_LENGTH | none | 0x1 |
_DDRF_RF0_MASK | none | 0x1 |
_DDRF_RF1_POSN | none | 0x1 |
_DDRF_RF1_POSITION | none | 0x1 |
_DDRF_RF1_SIZE | none | 0x1 |
_DDRF_RF1_LENGTH | none | 0x1 |
_DDRF_RF1_MASK | none | 0x2 |
_DDRF_RF2_POSN | none | 0x2 |
_DDRF_RF2_POSITION | none | 0x2 |
_DDRF_RF2_SIZE | none | 0x1 |
_DDRF_RF2_LENGTH | none | 0x1 |
_DDRF_RF2_MASK | none | 0x4 |
_DDRF_RF3_POSN | none | 0x3 |
_DDRF_RF3_POSITION | none | 0x3 |
_DDRF_RF3_SIZE | none | 0x1 |
_DDRF_RF3_LENGTH | none | 0x1 |
_DDRF_RF3_MASK | none | 0x8 |
_DDRF_RF4_POSN | none | 0x4 |
_DDRF_RF4_POSITION | none | 0x4 |
_DDRF_RF4_SIZE | none | 0x1 |
_DDRF_RF4_LENGTH | none | 0x1 |
_DDRF_RF4_MASK | none | 0x10 |
_DDRF_RF5_POSN | none | 0x5 |
_DDRF_RF5_POSITION | none | 0x5 |
_DDRF_RF5_SIZE | none | 0x1 |
_DDRF_RF5_LENGTH | none | 0x1 |
_DDRF_RF5_MASK | none | 0x20 |
_DDRF_RF6_POSN | none | 0x6 |
_DDRF_RF6_POSITION | none | 0x6 |
_DDRF_RF6_SIZE | none | 0x1 |
_DDRF_RF6_LENGTH | none | 0x1 |
_DDRF_RF6_MASK | none | 0x40 |
_DDRF_RF7_POSN | none | 0x7 |
_DDRF_RF7_POSITION | none | 0x7 |
_DDRF_RF7_SIZE | none | 0x1 |
_DDRF_RF7_LENGTH | none | 0x1 |
_DDRF_RF7_MASK | none | 0x80 |
TRISG | none | <\077435>TRISG |
TRISG | none | <\077435>TRISG |
_TRISG_TRISG0_POSN | none | 0x0 |
_TRISG_TRISG0_POSITION | none | 0x0 |
_TRISG_TRISG0_SIZE | none | 0x1 |
_TRISG_TRISG0_LENGTH | none | 0x1 |
_TRISG_TRISG0_MASK | none | 0x1 |
_TRISG_TRISG1_POSN | none | 0x1 |
_TRISG_TRISG1_POSITION | none | 0x1 |
_TRISG_TRISG1_SIZE | none | 0x1 |
_TRISG_TRISG1_LENGTH | none | 0x1 |
_TRISG_TRISG1_MASK | none | 0x2 |
_TRISG_TRISG2_POSN | none | 0x2 |
_TRISG_TRISG2_POSITION | none | 0x2 |
_TRISG_TRISG2_SIZE | none | 0x1 |
_TRISG_TRISG2_LENGTH | none | 0x1 |
_TRISG_TRISG2_MASK | none | 0x4 |
_TRISG_TRISG3_POSN | none | 0x3 |
_TRISG_TRISG3_POSITION | none | 0x3 |
_TRISG_TRISG3_SIZE | none | 0x1 |
_TRISG_TRISG3_LENGTH | none | 0x1 |
_TRISG_TRISG3_MASK | none | 0x8 |
_TRISG_TRISG4_POSN | none | 0x4 |
_TRISG_TRISG4_POSITION | none | 0x4 |
_TRISG_TRISG4_SIZE | none | 0x1 |
_TRISG_TRISG4_LENGTH | none | 0x1 |
_TRISG_TRISG4_MASK | none | 0x10 |
_TRISG_RG0_POSN | none | 0x0 |
_TRISG_RG0_POSITION | none | 0x0 |
_TRISG_RG0_SIZE | none | 0x1 |
_TRISG_RG0_LENGTH | none | 0x1 |
_TRISG_RG0_MASK | none | 0x1 |
_TRISG_RG1_POSN | none | 0x1 |
_TRISG_RG1_POSITION | none | 0x1 |
_TRISG_RG1_SIZE | none | 0x1 |
_TRISG_RG1_LENGTH | none | 0x1 |
_TRISG_RG1_MASK | none | 0x2 |
_TRISG_RG2_POSN | none | 0x2 |
_TRISG_RG2_POSITION | none | 0x2 |
_TRISG_RG2_SIZE | none | 0x1 |
_TRISG_RG2_LENGTH | none | 0x1 |
_TRISG_RG2_MASK | none | 0x4 |
_TRISG_RG3_POSN | none | 0x3 |
_TRISG_RG3_POSITION | none | 0x3 |
_TRISG_RG3_SIZE | none | 0x1 |
_TRISG_RG3_LENGTH | none | 0x1 |
_TRISG_RG3_MASK | none | 0x8 |
_TRISG_RG4_POSN | none | 0x4 |
_TRISG_RG4_POSITION | none | 0x4 |
_TRISG_RG4_SIZE | none | 0x1 |
_TRISG_RG4_LENGTH | none | 0x1 |
_TRISG_RG4_MASK | none | 0x10 |
_DDRG_TRISG0_POSN | none | 0x0 |
_DDRG_TRISG0_POSITION | none | 0x0 |
_DDRG_TRISG0_SIZE | none | 0x1 |
_DDRG_TRISG0_LENGTH | none | 0x1 |
_DDRG_TRISG0_MASK | none | 0x1 |
_DDRG_TRISG1_POSN | none | 0x1 |
_DDRG_TRISG1_POSITION | none | 0x1 |
_DDRG_TRISG1_SIZE | none | 0x1 |
_DDRG_TRISG1_LENGTH | none | 0x1 |
_DDRG_TRISG1_MASK | none | 0x2 |
_DDRG_TRISG2_POSN | none | 0x2 |
_DDRG_TRISG2_POSITION | none | 0x2 |
_DDRG_TRISG2_SIZE | none | 0x1 |
_DDRG_TRISG2_LENGTH | none | 0x1 |
_DDRG_TRISG2_MASK | none | 0x4 |
_DDRG_TRISG3_POSN | none | 0x3 |
_DDRG_TRISG3_POSITION | none | 0x3 |
_DDRG_TRISG3_SIZE | none | 0x1 |
_DDRG_TRISG3_LENGTH | none | 0x1 |
_DDRG_TRISG3_MASK | none | 0x8 |
_DDRG_TRISG4_POSN | none | 0x4 |
_DDRG_TRISG4_POSITION | none | 0x4 |
_DDRG_TRISG4_SIZE | none | 0x1 |
_DDRG_TRISG4_LENGTH | none | 0x1 |
_DDRG_TRISG4_MASK | none | 0x10 |
_DDRG_RG0_POSN | none | 0x0 |
_DDRG_RG0_POSITION | none | 0x0 |
_DDRG_RG0_SIZE | none | 0x1 |
_DDRG_RG0_LENGTH | none | 0x1 |
_DDRG_RG0_MASK | none | 0x1 |
_DDRG_RG1_POSN | none | 0x1 |
_DDRG_RG1_POSITION | none | 0x1 |
_DDRG_RG1_SIZE | none | 0x1 |
_DDRG_RG1_LENGTH | none | 0x1 |
_DDRG_RG1_MASK | none | 0x2 |
_DDRG_RG2_POSN | none | 0x2 |
_DDRG_RG2_POSITION | none | 0x2 |
_DDRG_RG2_SIZE | none | 0x1 |
_DDRG_RG2_LENGTH | none | 0x1 |
_DDRG_RG2_MASK | none | 0x4 |
_DDRG_RG3_POSN | none | 0x3 |
_DDRG_RG3_POSITION | none | 0x3 |
_DDRG_RG3_SIZE | none | 0x1 |
_DDRG_RG3_LENGTH | none | 0x1 |
_DDRG_RG3_MASK | none | 0x8 |
_DDRG_RG4_POSN | none | 0x4 |
_DDRG_RG4_POSITION | none | 0x4 |
_DDRG_RG4_SIZE | none | 0x1 |
_DDRG_RG4_LENGTH | none | 0x1 |
_DDRG_RG4_MASK | none | 0x10 |
TRISH | none | <\077435>TRISH |
TRISH | none | <\077435>TRISH |
_TRISH_TRISH0_POSN | none | 0x0 |
_TRISH_TRISH0_POSITION | none | 0x0 |
_TRISH_TRISH0_SIZE | none | 0x1 |
_TRISH_TRISH0_LENGTH | none | 0x1 |
_TRISH_TRISH0_MASK | none | 0x1 |
_TRISH_TRISH1_POSN | none | 0x1 |
_TRISH_TRISH1_POSITION | none | 0x1 |
_TRISH_TRISH1_SIZE | none | 0x1 |
_TRISH_TRISH1_LENGTH | none | 0x1 |
_TRISH_TRISH1_MASK | none | 0x2 |
_TRISH_TRISH2_POSN | none | 0x2 |
_TRISH_TRISH2_POSITION | none | 0x2 |
_TRISH_TRISH2_SIZE | none | 0x1 |
_TRISH_TRISH2_LENGTH | none | 0x1 |
_TRISH_TRISH2_MASK | none | 0x4 |
_TRISH_TRISH3_POSN | none | 0x3 |
_TRISH_TRISH3_POSITION | none | 0x3 |
_TRISH_TRISH3_SIZE | none | 0x1 |
_TRISH_TRISH3_LENGTH | none | 0x1 |
_TRISH_TRISH3_MASK | none | 0x8 |
_TRISH_TRISH4_POSN | none | 0x4 |
_TRISH_TRISH4_POSITION | none | 0x4 |
_TRISH_TRISH4_SIZE | none | 0x1 |
_TRISH_TRISH4_LENGTH | none | 0x1 |
_TRISH_TRISH4_MASK | none | 0x10 |
_TRISH_TRISH5_POSN | none | 0x5 |
_TRISH_TRISH5_POSITION | none | 0x5 |
_TRISH_TRISH5_SIZE | none | 0x1 |
_TRISH_TRISH5_LENGTH | none | 0x1 |
_TRISH_TRISH5_MASK | none | 0x20 |
_TRISH_TRISH6_POSN | none | 0x6 |
_TRISH_TRISH6_POSITION | none | 0x6 |
_TRISH_TRISH6_SIZE | none | 0x1 |
_TRISH_TRISH6_LENGTH | none | 0x1 |
_TRISH_TRISH6_MASK | none | 0x40 |
_TRISH_TRISH7_POSN | none | 0x7 |
_TRISH_TRISH7_POSITION | none | 0x7 |
_TRISH_TRISH7_SIZE | none | 0x1 |
_TRISH_TRISH7_LENGTH | none | 0x1 |
_TRISH_TRISH7_MASK | none | 0x80 |
_TRISH_RH0_POSN | none | 0x0 |
_TRISH_RH0_POSITION | none | 0x0 |
_TRISH_RH0_SIZE | none | 0x1 |
_TRISH_RH0_LENGTH | none | 0x1 |
_TRISH_RH0_MASK | none | 0x1 |
_TRISH_RH1_POSN | none | 0x1 |
_TRISH_RH1_POSITION | none | 0x1 |
_TRISH_RH1_SIZE | none | 0x1 |
_TRISH_RH1_LENGTH | none | 0x1 |
_TRISH_RH1_MASK | none | 0x2 |
_TRISH_RH2_POSN | none | 0x2 |
_TRISH_RH2_POSITION | none | 0x2 |
_TRISH_RH2_SIZE | none | 0x1 |
_TRISH_RH2_LENGTH | none | 0x1 |
_TRISH_RH2_MASK | none | 0x4 |
_TRISH_RH3_POSN | none | 0x3 |
_TRISH_RH3_POSITION | none | 0x3 |
_TRISH_RH3_SIZE | none | 0x1 |
_TRISH_RH3_LENGTH | none | 0x1 |
_TRISH_RH3_MASK | none | 0x8 |
_TRISH_RH4_POSN | none | 0x4 |
_TRISH_RH4_POSITION | none | 0x4 |
_TRISH_RH4_SIZE | none | 0x1 |
_TRISH_RH4_LENGTH | none | 0x1 |
_TRISH_RH4_MASK | none | 0x10 |
_TRISH_RH5_POSN | none | 0x5 |
_TRISH_RH5_POSITION | none | 0x5 |
_TRISH_RH5_SIZE | none | 0x1 |
_TRISH_RH5_LENGTH | none | 0x1 |
_TRISH_RH5_MASK | none | 0x20 |
_TRISH_RH6_POSN | none | 0x6 |
_TRISH_RH6_POSITION | none | 0x6 |
_TRISH_RH6_SIZE | none | 0x1 |
_TRISH_RH6_LENGTH | none | 0x1 |
_TRISH_RH6_MASK | none | 0x40 |
_TRISH_RH7_POSN | none | 0x7 |
_TRISH_RH7_POSITION | none | 0x7 |
_TRISH_RH7_SIZE | none | 0x1 |
_TRISH_RH7_LENGTH | none | 0x1 |
_TRISH_RH7_MASK | none | 0x80 |
_DDRH_TRISH0_POSN | none | 0x0 |
_DDRH_TRISH0_POSITION | none | 0x0 |
_DDRH_TRISH0_SIZE | none | 0x1 |
_DDRH_TRISH0_LENGTH | none | 0x1 |
_DDRH_TRISH0_MASK | none | 0x1 |
_DDRH_TRISH1_POSN | none | 0x1 |
_DDRH_TRISH1_POSITION | none | 0x1 |
_DDRH_TRISH1_SIZE | none | 0x1 |
_DDRH_TRISH1_LENGTH | none | 0x1 |
_DDRH_TRISH1_MASK | none | 0x2 |
_DDRH_TRISH2_POSN | none | 0x2 |
_DDRH_TRISH2_POSITION | none | 0x2 |
_DDRH_TRISH2_SIZE | none | 0x1 |
_DDRH_TRISH2_LENGTH | none | 0x1 |
_DDRH_TRISH2_MASK | none | 0x4 |
_DDRH_TRISH3_POSN | none | 0x3 |
_DDRH_TRISH3_POSITION | none | 0x3 |
_DDRH_TRISH3_SIZE | none | 0x1 |
_DDRH_TRISH3_LENGTH | none | 0x1 |
_DDRH_TRISH3_MASK | none | 0x8 |
_DDRH_TRISH4_POSN | none | 0x4 |
_DDRH_TRISH4_POSITION | none | 0x4 |
_DDRH_TRISH4_SIZE | none | 0x1 |
_DDRH_TRISH4_LENGTH | none | 0x1 |
_DDRH_TRISH4_MASK | none | 0x10 |
_DDRH_TRISH5_POSN | none | 0x5 |
_DDRH_TRISH5_POSITION | none | 0x5 |
_DDRH_TRISH5_SIZE | none | 0x1 |
_DDRH_TRISH5_LENGTH | none | 0x1 |
_DDRH_TRISH5_MASK | none | 0x20 |
_DDRH_TRISH6_POSN | none | 0x6 |
_DDRH_TRISH6_POSITION | none | 0x6 |
_DDRH_TRISH6_SIZE | none | 0x1 |
_DDRH_TRISH6_LENGTH | none | 0x1 |
_DDRH_TRISH6_MASK | none | 0x40 |
_DDRH_TRISH7_POSN | none | 0x7 |
_DDRH_TRISH7_POSITION | none | 0x7 |
_DDRH_TRISH7_SIZE | none | 0x1 |
_DDRH_TRISH7_LENGTH | none | 0x1 |
_DDRH_TRISH7_MASK | none | 0x80 |
_DDRH_RH0_POSN | none | 0x0 |
_DDRH_RH0_POSITION | none | 0x0 |
_DDRH_RH0_SIZE | none | 0x1 |
_DDRH_RH0_LENGTH | none | 0x1 |
_DDRH_RH0_MASK | none | 0x1 |
_DDRH_RH1_POSN | none | 0x1 |
_DDRH_RH1_POSITION | none | 0x1 |
_DDRH_RH1_SIZE | none | 0x1 |
_DDRH_RH1_LENGTH | none | 0x1 |
_DDRH_RH1_MASK | none | 0x2 |
_DDRH_RH2_POSN | none | 0x2 |
_DDRH_RH2_POSITION | none | 0x2 |
_DDRH_RH2_SIZE | none | 0x1 |
_DDRH_RH2_LENGTH | none | 0x1 |
_DDRH_RH2_MASK | none | 0x4 |
_DDRH_RH3_POSN | none | 0x3 |
_DDRH_RH3_POSITION | none | 0x3 |
_DDRH_RH3_SIZE | none | 0x1 |
_DDRH_RH3_LENGTH | none | 0x1 |
_DDRH_RH3_MASK | none | 0x8 |
_DDRH_RH4_POSN | none | 0x4 |
_DDRH_RH4_POSITION | none | 0x4 |
_DDRH_RH4_SIZE | none | 0x1 |
_DDRH_RH4_LENGTH | none | 0x1 |
_DDRH_RH4_MASK | none | 0x10 |
_DDRH_RH5_POSN | none | 0x5 |
_DDRH_RH5_POSITION | none | 0x5 |
_DDRH_RH5_SIZE | none | 0x1 |
_DDRH_RH5_LENGTH | none | 0x1 |
_DDRH_RH5_MASK | none | 0x20 |
_DDRH_RH6_POSN | none | 0x6 |
_DDRH_RH6_POSITION | none | 0x6 |
_DDRH_RH6_SIZE | none | 0x1 |
_DDRH_RH6_LENGTH | none | 0x1 |
_DDRH_RH6_MASK | none | 0x40 |
_DDRH_RH7_POSN | none | 0x7 |
_DDRH_RH7_POSITION | none | 0x7 |
_DDRH_RH7_SIZE | none | 0x1 |
_DDRH_RH7_LENGTH | none | 0x1 |
_DDRH_RH7_MASK | none | 0x80 |
TRISJ | none | <\077435>TRISJ |
TRISJ | none | <\077435>TRISJ |
_TRISJ_TRISJ0_POSN | none | 0x0 |
_TRISJ_TRISJ0_POSITION | none | 0x0 |
_TRISJ_TRISJ0_SIZE | none | 0x1 |
_TRISJ_TRISJ0_LENGTH | none | 0x1 |
_TRISJ_TRISJ0_MASK | none | 0x1 |
_TRISJ_TRISJ1_POSN | none | 0x1 |
_TRISJ_TRISJ1_POSITION | none | 0x1 |
_TRISJ_TRISJ1_SIZE | none | 0x1 |
_TRISJ_TRISJ1_LENGTH | none | 0x1 |
_TRISJ_TRISJ1_MASK | none | 0x2 |
_TRISJ_TRISJ2_POSN | none | 0x2 |
_TRISJ_TRISJ2_POSITION | none | 0x2 |
_TRISJ_TRISJ2_SIZE | none | 0x1 |
_TRISJ_TRISJ2_LENGTH | none | 0x1 |
_TRISJ_TRISJ2_MASK | none | 0x4 |
_TRISJ_TRISJ3_POSN | none | 0x3 |
_TRISJ_TRISJ3_POSITION | none | 0x3 |
_TRISJ_TRISJ3_SIZE | none | 0x1 |
_TRISJ_TRISJ3_LENGTH | none | 0x1 |
_TRISJ_TRISJ3_MASK | none | 0x8 |
_TRISJ_TRISJ4_POSN | none | 0x4 |
_TRISJ_TRISJ4_POSITION | none | 0x4 |
_TRISJ_TRISJ4_SIZE | none | 0x1 |
_TRISJ_TRISJ4_LENGTH | none | 0x1 |
_TRISJ_TRISJ4_MASK | none | 0x10 |
_TRISJ_TRISJ5_POSN | none | 0x5 |
_TRISJ_TRISJ5_POSITION | none | 0x5 |
_TRISJ_TRISJ5_SIZE | none | 0x1 |
_TRISJ_TRISJ5_LENGTH | none | 0x1 |
_TRISJ_TRISJ5_MASK | none | 0x20 |
_TRISJ_TRISJ6_POSN | none | 0x6 |
_TRISJ_TRISJ6_POSITION | none | 0x6 |
_TRISJ_TRISJ6_SIZE | none | 0x1 |
_TRISJ_TRISJ6_LENGTH | none | 0x1 |
_TRISJ_TRISJ6_MASK | none | 0x40 |
_TRISJ_TRISJ7_POSN | none | 0x7 |
_TRISJ_TRISJ7_POSITION | none | 0x7 |
_TRISJ_TRISJ7_SIZE | none | 0x1 |
_TRISJ_TRISJ7_LENGTH | none | 0x1 |
_TRISJ_TRISJ7_MASK | none | 0x80 |
_TRISJ_RJ0_POSN | none | 0x0 |
_TRISJ_RJ0_POSITION | none | 0x0 |
_TRISJ_RJ0_SIZE | none | 0x1 |
_TRISJ_RJ0_LENGTH | none | 0x1 |
_TRISJ_RJ0_MASK | none | 0x1 |
_TRISJ_RJ1_POSN | none | 0x1 |
_TRISJ_RJ1_POSITION | none | 0x1 |
_TRISJ_RJ1_SIZE | none | 0x1 |
_TRISJ_RJ1_LENGTH | none | 0x1 |
_TRISJ_RJ1_MASK | none | 0x2 |
_TRISJ_RJ2_POSN | none | 0x2 |
_TRISJ_RJ2_POSITION | none | 0x2 |
_TRISJ_RJ2_SIZE | none | 0x1 |
_TRISJ_RJ2_LENGTH | none | 0x1 |
_TRISJ_RJ2_MASK | none | 0x4 |
_TRISJ_RJ3_POSN | none | 0x3 |
_TRISJ_RJ3_POSITION | none | 0x3 |
_TRISJ_RJ3_SIZE | none | 0x1 |
_TRISJ_RJ3_LENGTH | none | 0x1 |
_TRISJ_RJ3_MASK | none | 0x8 |
_TRISJ_RJ4_POSN | none | 0x4 |
_TRISJ_RJ4_POSITION | none | 0x4 |
_TRISJ_RJ4_SIZE | none | 0x1 |
_TRISJ_RJ4_LENGTH | none | 0x1 |
_TRISJ_RJ4_MASK | none | 0x10 |
_TRISJ_RJ5_POSN | none | 0x5 |
_TRISJ_RJ5_POSITION | none | 0x5 |
_TRISJ_RJ5_SIZE | none | 0x1 |
_TRISJ_RJ5_LENGTH | none | 0x1 |
_TRISJ_RJ5_MASK | none | 0x20 |
_TRISJ_RJ6_POSN | none | 0x6 |
_TRISJ_RJ6_POSITION | none | 0x6 |
_TRISJ_RJ6_SIZE | none | 0x1 |
_TRISJ_RJ6_LENGTH | none | 0x1 |
_TRISJ_RJ6_MASK | none | 0x40 |
_TRISJ_RJ7_POSN | none | 0x7 |
_TRISJ_RJ7_POSITION | none | 0x7 |
_TRISJ_RJ7_SIZE | none | 0x1 |
_TRISJ_RJ7_LENGTH | none | 0x1 |
_TRISJ_RJ7_MASK | none | 0x80 |
_DDRJ_TRISJ0_POSN | none | 0x0 |
_DDRJ_TRISJ0_POSITION | none | 0x0 |
_DDRJ_TRISJ0_SIZE | none | 0x1 |
_DDRJ_TRISJ0_LENGTH | none | 0x1 |
_DDRJ_TRISJ0_MASK | none | 0x1 |
_DDRJ_TRISJ1_POSN | none | 0x1 |
_DDRJ_TRISJ1_POSITION | none | 0x1 |
_DDRJ_TRISJ1_SIZE | none | 0x1 |
_DDRJ_TRISJ1_LENGTH | none | 0x1 |
_DDRJ_TRISJ1_MASK | none | 0x2 |
_DDRJ_TRISJ2_POSN | none | 0x2 |
_DDRJ_TRISJ2_POSITION | none | 0x2 |
_DDRJ_TRISJ2_SIZE | none | 0x1 |
_DDRJ_TRISJ2_LENGTH | none | 0x1 |
_DDRJ_TRISJ2_MASK | none | 0x4 |
_DDRJ_TRISJ3_POSN | none | 0x3 |
_DDRJ_TRISJ3_POSITION | none | 0x3 |
_DDRJ_TRISJ3_SIZE | none | 0x1 |
_DDRJ_TRISJ3_LENGTH | none | 0x1 |
_DDRJ_TRISJ3_MASK | none | 0x8 |
_DDRJ_TRISJ4_POSN | none | 0x4 |
_DDRJ_TRISJ4_POSITION | none | 0x4 |
_DDRJ_TRISJ4_SIZE | none | 0x1 |
_DDRJ_TRISJ4_LENGTH | none | 0x1 |
_DDRJ_TRISJ4_MASK | none | 0x10 |
_DDRJ_TRISJ5_POSN | none | 0x5 |
_DDRJ_TRISJ5_POSITION | none | 0x5 |
_DDRJ_TRISJ5_SIZE | none | 0x1 |
_DDRJ_TRISJ5_LENGTH | none | 0x1 |
_DDRJ_TRISJ5_MASK | none | 0x20 |
_DDRJ_TRISJ6_POSN | none | 0x6 |
_DDRJ_TRISJ6_POSITION | none | 0x6 |
_DDRJ_TRISJ6_SIZE | none | 0x1 |
_DDRJ_TRISJ6_LENGTH | none | 0x1 |
_DDRJ_TRISJ6_MASK | none | 0x40 |
_DDRJ_TRISJ7_POSN | none | 0x7 |
_DDRJ_TRISJ7_POSITION | none | 0x7 |
_DDRJ_TRISJ7_SIZE | none | 0x1 |
_DDRJ_TRISJ7_LENGTH | none | 0x1 |
_DDRJ_TRISJ7_MASK | none | 0x80 |
_DDRJ_RJ0_POSN | none | 0x0 |
_DDRJ_RJ0_POSITION | none | 0x0 |
_DDRJ_RJ0_SIZE | none | 0x1 |
_DDRJ_RJ0_LENGTH | none | 0x1 |
_DDRJ_RJ0_MASK | none | 0x1 |
_DDRJ_RJ1_POSN | none | 0x1 |
_DDRJ_RJ1_POSITION | none | 0x1 |
_DDRJ_RJ1_SIZE | none | 0x1 |
_DDRJ_RJ1_LENGTH | none | 0x1 |
_DDRJ_RJ1_MASK | none | 0x2 |
_DDRJ_RJ2_POSN | none | 0x2 |
_DDRJ_RJ2_POSITION | none | 0x2 |
_DDRJ_RJ2_SIZE | none | 0x1 |
_DDRJ_RJ2_LENGTH | none | 0x1 |
_DDRJ_RJ2_MASK | none | 0x4 |
_DDRJ_RJ3_POSN | none | 0x3 |
_DDRJ_RJ3_POSITION | none | 0x3 |
_DDRJ_RJ3_SIZE | none | 0x1 |
_DDRJ_RJ3_LENGTH | none | 0x1 |
_DDRJ_RJ3_MASK | none | 0x8 |
_DDRJ_RJ4_POSN | none | 0x4 |
_DDRJ_RJ4_POSITION | none | 0x4 |
_DDRJ_RJ4_SIZE | none | 0x1 |
_DDRJ_RJ4_LENGTH | none | 0x1 |
_DDRJ_RJ4_MASK | none | 0x10 |
_DDRJ_RJ5_POSN | none | 0x5 |
_DDRJ_RJ5_POSITION | none | 0x5 |
_DDRJ_RJ5_SIZE | none | 0x1 |
_DDRJ_RJ5_LENGTH | none | 0x1 |
_DDRJ_RJ5_MASK | none | 0x20 |
_DDRJ_RJ6_POSN | none | 0x6 |
_DDRJ_RJ6_POSITION | none | 0x6 |
_DDRJ_RJ6_SIZE | none | 0x1 |
_DDRJ_RJ6_LENGTH | none | 0x1 |
_DDRJ_RJ6_MASK | none | 0x40 |
_DDRJ_RJ7_POSN | none | 0x7 |
_DDRJ_RJ7_POSITION | none | 0x7 |
_DDRJ_RJ7_SIZE | none | 0x1 |
_DDRJ_RJ7_LENGTH | none | 0x1 |
_DDRJ_RJ7_MASK | none | 0x80 |
MEMCON | none | <\077435>MEMCON |
MEMCON | none | <\077435>MEMCON |
_MEMCON_WM_POSN | none | 0x0 |
_MEMCON_WM_POSITION | none | 0x0 |
_MEMCON_WM_SIZE | none | 0x2 |
_MEMCON_WM_LENGTH | none | 0x2 |
_MEMCON_WM_MASK | none | 0x3 |
_MEMCON_WAIT_POSN | none | 0x4 |
_MEMCON_WAIT_POSITION | none | 0x4 |
_MEMCON_WAIT_SIZE | none | 0x2 |
_MEMCON_WAIT_LENGTH | none | 0x2 |
_MEMCON_WAIT_MASK | none | 0x30 |
_MEMCON_EBDIS_POSN | none | 0x7 |
_MEMCON_EBDIS_POSITION | none | 0x7 |
_MEMCON_EBDIS_SIZE | none | 0x1 |
_MEMCON_EBDIS_LENGTH | none | 0x1 |
_MEMCON_EBDIS_MASK | none | 0x80 |
_MEMCON_WM0_POSN | none | 0x0 |
_MEMCON_WM0_POSITION | none | 0x0 |
_MEMCON_WM0_SIZE | none | 0x1 |
_MEMCON_WM0_LENGTH | none | 0x1 |
_MEMCON_WM0_MASK | none | 0x1 |
_MEMCON_WM1_POSN | none | 0x1 |
_MEMCON_WM1_POSITION | none | 0x1 |
_MEMCON_WM1_SIZE | none | 0x1 |
_MEMCON_WM1_LENGTH | none | 0x1 |
_MEMCON_WM1_MASK | none | 0x2 |
_MEMCON_WAIT0_POSN | none | 0x4 |
_MEMCON_WAIT0_POSITION | none | 0x4 |
_MEMCON_WAIT0_SIZE | none | 0x1 |
_MEMCON_WAIT0_LENGTH | none | 0x1 |
_MEMCON_WAIT0_MASK | none | 0x10 |
_MEMCON_WAIT1_POSN | none | 0x5 |
_MEMCON_WAIT1_POSITION | none | 0x5 |
_MEMCON_WAIT1_SIZE | none | 0x1 |
_MEMCON_WAIT1_LENGTH | none | 0x1 |
_MEMCON_WAIT1_MASK | none | 0x20 |
PIE1 | none | <\077435>PIE1 |
PIE1 | none | <\077435>PIE1 |
_PIE1_TMR1IE_POSN | none | 0x0 |
_PIE1_TMR1IE_POSITION | none | 0x0 |
_PIE1_TMR1IE_SIZE | none | 0x1 |
_PIE1_TMR1IE_LENGTH | none | 0x1 |
_PIE1_TMR1IE_MASK | none | 0x1 |
_PIE1_TMR2IE_POSN | none | 0x1 |
_PIE1_TMR2IE_POSITION | none | 0x1 |
_PIE1_TMR2IE_SIZE | none | 0x1 |
_PIE1_TMR2IE_LENGTH | none | 0x1 |
_PIE1_TMR2IE_MASK | none | 0x2 |
_PIE1_CCP1IE_POSN | none | 0x2 |
_PIE1_CCP1IE_POSITION | none | 0x2 |
_PIE1_CCP1IE_SIZE | none | 0x1 |
_PIE1_CCP1IE_LENGTH | none | 0x1 |
_PIE1_CCP1IE_MASK | none | 0x4 |
_PIE1_SSPIE_POSN | none | 0x3 |
_PIE1_SSPIE_POSITION | none | 0x3 |
_PIE1_SSPIE_SIZE | none | 0x1 |
_PIE1_SSPIE_LENGTH | none | 0x1 |
_PIE1_SSPIE_MASK | none | 0x8 |
_PIE1_TXIE_POSN | none | 0x4 |
_PIE1_TXIE_POSITION | none | 0x4 |
_PIE1_TXIE_SIZE | none | 0x1 |
_PIE1_TXIE_LENGTH | none | 0x1 |
_PIE1_TXIE_MASK | none | 0x10 |
_PIE1_RCIE_POSN | none | 0x5 |
_PIE1_RCIE_POSITION | none | 0x5 |
_PIE1_RCIE_SIZE | none | 0x1 |
_PIE1_RCIE_LENGTH | none | 0x1 |
_PIE1_RCIE_MASK | none | 0x20 |
_PIE1_ADIE_POSN | none | 0x6 |
_PIE1_ADIE_POSITION | none | 0x6 |
_PIE1_ADIE_SIZE | none | 0x1 |
_PIE1_ADIE_LENGTH | none | 0x1 |
_PIE1_ADIE_MASK | none | 0x40 |
_PIE1_PSPIE_POSN | none | 0x7 |
_PIE1_PSPIE_POSITION | none | 0x7 |
_PIE1_PSPIE_SIZE | none | 0x1 |
_PIE1_PSPIE_LENGTH | none | 0x1 |
_PIE1_PSPIE_MASK | none | 0x80 |
_PIE1_TX1IE_POSN | none | 0x4 |
_PIE1_TX1IE_POSITION | none | 0x4 |
_PIE1_TX1IE_SIZE | none | 0x1 |
_PIE1_TX1IE_LENGTH | none | 0x1 |
_PIE1_TX1IE_MASK | none | 0x10 |
_PIE1_RC1IE_POSN | none | 0x5 |
_PIE1_RC1IE_POSITION | none | 0x5 |
_PIE1_RC1IE_SIZE | none | 0x1 |
_PIE1_RC1IE_LENGTH | none | 0x1 |
_PIE1_RC1IE_MASK | none | 0x20 |
PIR1 | none | <\077435>PIR1 |
PIR1 | none | <\077435>PIR1 |
_PIR1_TMR1IF_POSN | none | 0x0 |
_PIR1_TMR1IF_POSITION | none | 0x0 |
_PIR1_TMR1IF_SIZE | none | 0x1 |
_PIR1_TMR1IF_LENGTH | none | 0x1 |
_PIR1_TMR1IF_MASK | none | 0x1 |
_PIR1_TMR2IF_POSN | none | 0x1 |
_PIR1_TMR2IF_POSITION | none | 0x1 |
_PIR1_TMR2IF_SIZE | none | 0x1 |
_PIR1_TMR2IF_LENGTH | none | 0x1 |
_PIR1_TMR2IF_MASK | none | 0x2 |
_PIR1_CCP1IF_POSN | none | 0x2 |
_PIR1_CCP1IF_POSITION | none | 0x2 |
_PIR1_CCP1IF_SIZE | none | 0x1 |
_PIR1_CCP1IF_LENGTH | none | 0x1 |
_PIR1_CCP1IF_MASK | none | 0x4 |
_PIR1_SSPIF_POSN | none | 0x3 |
_PIR1_SSPIF_POSITION | none | 0x3 |
_PIR1_SSPIF_SIZE | none | 0x1 |
_PIR1_SSPIF_LENGTH | none | 0x1 |
_PIR1_SSPIF_MASK | none | 0x8 |
_PIR1_TXIF_POSN | none | 0x4 |
_PIR1_TXIF_POSITION | none | 0x4 |
_PIR1_TXIF_SIZE | none | 0x1 |
_PIR1_TXIF_LENGTH | none | 0x1 |
_PIR1_TXIF_MASK | none | 0x10 |
_PIR1_RCIF_POSN | none | 0x5 |
_PIR1_RCIF_POSITION | none | 0x5 |
_PIR1_RCIF_SIZE | none | 0x1 |
_PIR1_RCIF_LENGTH | none | 0x1 |
_PIR1_RCIF_MASK | none | 0x20 |
_PIR1_ADIF_POSN | none | 0x6 |
_PIR1_ADIF_POSITION | none | 0x6 |
_PIR1_ADIF_SIZE | none | 0x1 |
_PIR1_ADIF_LENGTH | none | 0x1 |
_PIR1_ADIF_MASK | none | 0x40 |
_PIR1_PSPIF_POSN | none | 0x7 |
_PIR1_PSPIF_POSITION | none | 0x7 |
_PIR1_PSPIF_SIZE | none | 0x1 |
_PIR1_PSPIF_LENGTH | none | 0x1 |
_PIR1_PSPIF_MASK | none | 0x80 |
_PIR1_TX1IF_POSN | none | 0x4 |
_PIR1_TX1IF_POSITION | none | 0x4 |
_PIR1_TX1IF_SIZE | none | 0x1 |
_PIR1_TX1IF_LENGTH | none | 0x1 |
_PIR1_TX1IF_MASK | none | 0x10 |
_PIR1_RC1IF_POSN | none | 0x5 |
_PIR1_RC1IF_POSITION | none | 0x5 |
_PIR1_RC1IF_SIZE | none | 0x1 |
_PIR1_RC1IF_LENGTH | none | 0x1 |
_PIR1_RC1IF_MASK | none | 0x20 |
IPR1 | none | <\077435>IPR1 |
IPR1 | none | <\077435>IPR1 |
_IPR1_TMR1IP_POSN | none | 0x0 |
_IPR1_TMR1IP_POSITION | none | 0x0 |
_IPR1_TMR1IP_SIZE | none | 0x1 |
_IPR1_TMR1IP_LENGTH | none | 0x1 |
_IPR1_TMR1IP_MASK | none | 0x1 |
_IPR1_TMR2IP_POSN | none | 0x1 |
_IPR1_TMR2IP_POSITION | none | 0x1 |
_IPR1_TMR2IP_SIZE | none | 0x1 |
_IPR1_TMR2IP_LENGTH | none | 0x1 |
_IPR1_TMR2IP_MASK | none | 0x2 |
_IPR1_CCP1IP_POSN | none | 0x2 |
_IPR1_CCP1IP_POSITION | none | 0x2 |
_IPR1_CCP1IP_SIZE | none | 0x1 |
_IPR1_CCP1IP_LENGTH | none | 0x1 |
_IPR1_CCP1IP_MASK | none | 0x4 |
_IPR1_SSPIP_POSN | none | 0x3 |
_IPR1_SSPIP_POSITION | none | 0x3 |
_IPR1_SSPIP_SIZE | none | 0x1 |
_IPR1_SSPIP_LENGTH | none | 0x1 |
_IPR1_SSPIP_MASK | none | 0x8 |
_IPR1_TXIP_POSN | none | 0x4 |
_IPR1_TXIP_POSITION | none | 0x4 |
_IPR1_TXIP_SIZE | none | 0x1 |
_IPR1_TXIP_LENGTH | none | 0x1 |
_IPR1_TXIP_MASK | none | 0x10 |
_IPR1_RCIP_POSN | none | 0x5 |
_IPR1_RCIP_POSITION | none | 0x5 |
_IPR1_RCIP_SIZE | none | 0x1 |
_IPR1_RCIP_LENGTH | none | 0x1 |
_IPR1_RCIP_MASK | none | 0x20 |
_IPR1_ADIP_POSN | none | 0x6 |
_IPR1_ADIP_POSITION | none | 0x6 |
_IPR1_ADIP_SIZE | none | 0x1 |
_IPR1_ADIP_LENGTH | none | 0x1 |
_IPR1_ADIP_MASK | none | 0x40 |
_IPR1_PSPIP_POSN | none | 0x7 |
_IPR1_PSPIP_POSITION | none | 0x7 |
_IPR1_PSPIP_SIZE | none | 0x1 |
_IPR1_PSPIP_LENGTH | none | 0x1 |
_IPR1_PSPIP_MASK | none | 0x80 |
_IPR1_TX1IP_POSN | none | 0x4 |
_IPR1_TX1IP_POSITION | none | 0x4 |
_IPR1_TX1IP_SIZE | none | 0x1 |
_IPR1_TX1IP_LENGTH | none | 0x1 |
_IPR1_TX1IP_MASK | none | 0x10 |
_IPR1_RC1IP_POSN | none | 0x5 |
_IPR1_RC1IP_POSITION | none | 0x5 |
_IPR1_RC1IP_SIZE | none | 0x1 |
_IPR1_RC1IP_LENGTH | none | 0x1 |
_IPR1_RC1IP_MASK | none | 0x20 |
PIE2 | none | <\077435>PIE2 |
PIE2 | none | <\077435>PIE2 |
_PIE2_CCP2IE_POSN | none | 0x0 |
_PIE2_CCP2IE_POSITION | none | 0x0 |
_PIE2_CCP2IE_SIZE | none | 0x1 |
_PIE2_CCP2IE_LENGTH | none | 0x1 |
_PIE2_CCP2IE_MASK | none | 0x1 |
_PIE2_TMR3IE_POSN | none | 0x1 |
_PIE2_TMR3IE_POSITION | none | 0x1 |
_PIE2_TMR3IE_SIZE | none | 0x1 |
_PIE2_TMR3IE_LENGTH | none | 0x1 |
_PIE2_TMR3IE_MASK | none | 0x2 |
_PIE2_LVDIE_POSN | none | 0x2 |
_PIE2_LVDIE_POSITION | none | 0x2 |
_PIE2_LVDIE_SIZE | none | 0x1 |
_PIE2_LVDIE_LENGTH | none | 0x1 |
_PIE2_LVDIE_MASK | none | 0x4 |
_PIE2_BCLIE_POSN | none | 0x3 |
_PIE2_BCLIE_POSITION | none | 0x3 |
_PIE2_BCLIE_SIZE | none | 0x1 |
_PIE2_BCLIE_LENGTH | none | 0x1 |
_PIE2_BCLIE_MASK | none | 0x8 |
_PIE2_EEIE_POSN | none | 0x4 |
_PIE2_EEIE_POSITION | none | 0x4 |
_PIE2_EEIE_SIZE | none | 0x1 |
_PIE2_EEIE_LENGTH | none | 0x1 |
_PIE2_EEIE_MASK | none | 0x10 |
_PIE2_CMIE_POSN | none | 0x6 |
_PIE2_CMIE_POSITION | none | 0x6 |
_PIE2_CMIE_SIZE | none | 0x1 |
_PIE2_CMIE_LENGTH | none | 0x1 |
_PIE2_CMIE_MASK | none | 0x40 |
PIR2 | none | <\077435>PIR2 |
PIR2 | none | <\077435>PIR2 |
_PIR2_CCP2IF_POSN | none | 0x0 |
_PIR2_CCP2IF_POSITION | none | 0x0 |
_PIR2_CCP2IF_SIZE | none | 0x1 |
_PIR2_CCP2IF_LENGTH | none | 0x1 |
_PIR2_CCP2IF_MASK | none | 0x1 |
_PIR2_TMR3IF_POSN | none | 0x1 |
_PIR2_TMR3IF_POSITION | none | 0x1 |
_PIR2_TMR3IF_SIZE | none | 0x1 |
_PIR2_TMR3IF_LENGTH | none | 0x1 |
_PIR2_TMR3IF_MASK | none | 0x2 |
_PIR2_LVDIF_POSN | none | 0x2 |
_PIR2_LVDIF_POSITION | none | 0x2 |
_PIR2_LVDIF_SIZE | none | 0x1 |
_PIR2_LVDIF_LENGTH | none | 0x1 |
_PIR2_LVDIF_MASK | none | 0x4 |
_PIR2_BCLIF_POSN | none | 0x3 |
_PIR2_BCLIF_POSITION | none | 0x3 |
_PIR2_BCLIF_SIZE | none | 0x1 |
_PIR2_BCLIF_LENGTH | none | 0x1 |
_PIR2_BCLIF_MASK | none | 0x8 |
_PIR2_EEIF_POSN | none | 0x4 |
_PIR2_EEIF_POSITION | none | 0x4 |
_PIR2_EEIF_SIZE | none | 0x1 |
_PIR2_EEIF_LENGTH | none | 0x1 |
_PIR2_EEIF_MASK | none | 0x10 |
_PIR2_CMIF_POSN | none | 0x6 |
_PIR2_CMIF_POSITION | none | 0x6 |
_PIR2_CMIF_SIZE | none | 0x1 |
_PIR2_CMIF_LENGTH | none | 0x1 |
_PIR2_CMIF_MASK | none | 0x40 |
IPR2 | none | <\077435>IPR2 |
IPR2 | none | <\077435>IPR2 |
_IPR2_CCP2IP_POSN | none | 0x0 |
_IPR2_CCP2IP_POSITION | none | 0x0 |
_IPR2_CCP2IP_SIZE | none | 0x1 |
_IPR2_CCP2IP_LENGTH | none | 0x1 |
_IPR2_CCP2IP_MASK | none | 0x1 |
_IPR2_TMR3IP_POSN | none | 0x1 |
_IPR2_TMR3IP_POSITION | none | 0x1 |
_IPR2_TMR3IP_SIZE | none | 0x1 |
_IPR2_TMR3IP_LENGTH | none | 0x1 |
_IPR2_TMR3IP_MASK | none | 0x2 |
_IPR2_LVDIP_POSN | none | 0x2 |
_IPR2_LVDIP_POSITION | none | 0x2 |
_IPR2_LVDIP_SIZE | none | 0x1 |
_IPR2_LVDIP_LENGTH | none | 0x1 |
_IPR2_LVDIP_MASK | none | 0x4 |
_IPR2_BCLIP_POSN | none | 0x3 |
_IPR2_BCLIP_POSITION | none | 0x3 |
_IPR2_BCLIP_SIZE | none | 0x1 |
_IPR2_BCLIP_LENGTH | none | 0x1 |
_IPR2_BCLIP_MASK | none | 0x8 |
_IPR2_EEIP_POSN | none | 0x4 |
_IPR2_EEIP_POSITION | none | 0x4 |
_IPR2_EEIP_SIZE | none | 0x1 |
_IPR2_EEIP_LENGTH | none | 0x1 |
_IPR2_EEIP_MASK | none | 0x10 |
_IPR2_CMIP_POSN | none | 0x6 |
_IPR2_CMIP_POSITION | none | 0x6 |
_IPR2_CMIP_SIZE | none | 0x1 |
_IPR2_CMIP_LENGTH | none | 0x1 |
_IPR2_CMIP_MASK | none | 0x40 |
PIE3 | none | <\077435>PIE3 |
PIE3 | none | <\077435>PIE3 |
_PIE3_CCP3IE_POSN | none | 0x0 |
_PIE3_CCP3IE_POSITION | none | 0x0 |
_PIE3_CCP3IE_SIZE | none | 0x1 |
_PIE3_CCP3IE_LENGTH | none | 0x1 |
_PIE3_CCP3IE_MASK | none | 0x1 |
_PIE3_CCP4IE_POSN | none | 0x1 |
_PIE3_CCP4IE_POSITION | none | 0x1 |
_PIE3_CCP4IE_SIZE | none | 0x1 |
_PIE3_CCP4IE_LENGTH | none | 0x1 |
_PIE3_CCP4IE_MASK | none | 0x2 |
_PIE3_CCP5IE_POSN | none | 0x2 |
_PIE3_CCP5IE_POSITION | none | 0x2 |
_PIE3_CCP5IE_SIZE | none | 0x1 |
_PIE3_CCP5IE_LENGTH | none | 0x1 |
_PIE3_CCP5IE_MASK | none | 0x4 |
_PIE3_TMR4IE_POSN | none | 0x3 |
_PIE3_TMR4IE_POSITION | none | 0x3 |
_PIE3_TMR4IE_SIZE | none | 0x1 |
_PIE3_TMR4IE_LENGTH | none | 0x1 |
_PIE3_TMR4IE_MASK | none | 0x8 |
_PIE3_TX2IE_POSN | none | 0x4 |
_PIE3_TX2IE_POSITION | none | 0x4 |
_PIE3_TX2IE_SIZE | none | 0x1 |
_PIE3_TX2IE_LENGTH | none | 0x1 |
_PIE3_TX2IE_MASK | none | 0x10 |
_PIE3_RC2IE_POSN | none | 0x5 |
_PIE3_RC2IE_POSITION | none | 0x5 |
_PIE3_RC2IE_SIZE | none | 0x1 |
_PIE3_RC2IE_LENGTH | none | 0x1 |
_PIE3_RC2IE_MASK | none | 0x20 |
_PIE3_RXB0IE_POSN | none | 0x0 |
_PIE3_RXB0IE_POSITION | none | 0x0 |
_PIE3_RXB0IE_SIZE | none | 0x1 |
_PIE3_RXB0IE_LENGTH | none | 0x1 |
_PIE3_RXB0IE_MASK | none | 0x1 |
_PIE3_RXB1IE_POSN | none | 0x1 |
_PIE3_RXB1IE_POSITION | none | 0x1 |
_PIE3_RXB1IE_SIZE | none | 0x1 |
_PIE3_RXB1IE_LENGTH | none | 0x1 |
_PIE3_RXB1IE_MASK | none | 0x2 |
_PIE3_TXB0IE_POSN | none | 0x2 |
_PIE3_TXB0IE_POSITION | none | 0x2 |
_PIE3_TXB0IE_SIZE | none | 0x1 |
_PIE3_TXB0IE_LENGTH | none | 0x1 |
_PIE3_TXB0IE_MASK | none | 0x4 |
_PIE3_TXB1IE_POSN | none | 0x3 |
_PIE3_TXB1IE_POSITION | none | 0x3 |
_PIE3_TXB1IE_SIZE | none | 0x1 |
_PIE3_TXB1IE_LENGTH | none | 0x1 |
_PIE3_TXB1IE_MASK | none | 0x8 |
_PIE3_TXB2IE_POSN | none | 0x4 |
_PIE3_TXB2IE_POSITION | none | 0x4 |
_PIE3_TXB2IE_SIZE | none | 0x1 |
_PIE3_TXB2IE_LENGTH | none | 0x1 |
_PIE3_TXB2IE_MASK | none | 0x10 |
_PIE3_RXBNIE_POSN | none | 0x1 |
_PIE3_RXBNIE_POSITION | none | 0x1 |
_PIE3_RXBNIE_SIZE | none | 0x1 |
_PIE3_RXBNIE_LENGTH | none | 0x1 |
_PIE3_RXBNIE_MASK | none | 0x2 |
_PIE3_TXBNIE_POSN | none | 0x4 |
_PIE3_TXBNIE_POSITION | none | 0x4 |
_PIE3_TXBNIE_SIZE | none | 0x1 |
_PIE3_TXBNIE_LENGTH | none | 0x1 |
_PIE3_TXBNIE_MASK | none | 0x10 |
PIR3 | none | <\077435>PIR3 |
PIR3 | none | <\077435>PIR3 |
_PIR3_CCP3IF_POSN | none | 0x0 |
_PIR3_CCP3IF_POSITION | none | 0x0 |
_PIR3_CCP3IF_SIZE | none | 0x1 |
_PIR3_CCP3IF_LENGTH | none | 0x1 |
_PIR3_CCP3IF_MASK | none | 0x1 |
_PIR3_CCP4IF_POSN | none | 0x1 |
_PIR3_CCP4IF_POSITION | none | 0x1 |
_PIR3_CCP4IF_SIZE | none | 0x1 |
_PIR3_CCP4IF_LENGTH | none | 0x1 |
_PIR3_CCP4IF_MASK | none | 0x2 |
_PIR3_CCP5IF_POSN | none | 0x2 |
_PIR3_CCP5IF_POSITION | none | 0x2 |
_PIR3_CCP5IF_SIZE | none | 0x1 |
_PIR3_CCP5IF_LENGTH | none | 0x1 |
_PIR3_CCP5IF_MASK | none | 0x4 |
_PIR3_TMR4IF_POSN | none | 0x3 |
_PIR3_TMR4IF_POSITION | none | 0x3 |
_PIR3_TMR4IF_SIZE | none | 0x1 |
_PIR3_TMR4IF_LENGTH | none | 0x1 |
_PIR3_TMR4IF_MASK | none | 0x8 |
_PIR3_TX2IF_POSN | none | 0x4 |
_PIR3_TX2IF_POSITION | none | 0x4 |
_PIR3_TX2IF_SIZE | none | 0x1 |
_PIR3_TX2IF_LENGTH | none | 0x1 |
_PIR3_TX2IF_MASK | none | 0x10 |
_PIR3_RC2IF_POSN | none | 0x5 |
_PIR3_RC2IF_POSITION | none | 0x5 |
_PIR3_RC2IF_SIZE | none | 0x1 |
_PIR3_RC2IF_LENGTH | none | 0x1 |
_PIR3_RC2IF_MASK | none | 0x20 |
_PIR3_RXBNIF_POSN | none | 0x1 |
_PIR3_RXBNIF_POSITION | none | 0x1 |
_PIR3_RXBNIF_SIZE | none | 0x1 |
_PIR3_RXBNIF_LENGTH | none | 0x1 |
_PIR3_RXBNIF_MASK | none | 0x2 |
_PIR3_TXBNIF_POSN | none | 0x4 |
_PIR3_TXBNIF_POSITION | none | 0x4 |
_PIR3_TXBNIF_SIZE | none | 0x1 |
_PIR3_TXBNIF_LENGTH | none | 0x1 |
_PIR3_TXBNIF_MASK | none | 0x10 |
IPR3 | none | <\077435>IPR3 |
IPR3 | none | <\077435>IPR3 |
_IPR3_CCP3IP_POSN | none | 0x0 |
_IPR3_CCP3IP_POSITION | none | 0x0 |
_IPR3_CCP3IP_SIZE | none | 0x1 |
_IPR3_CCP3IP_LENGTH | none | 0x1 |
_IPR3_CCP3IP_MASK | none | 0x1 |
_IPR3_CCP4IP_POSN | none | 0x1 |
_IPR3_CCP4IP_POSITION | none | 0x1 |
_IPR3_CCP4IP_SIZE | none | 0x1 |
_IPR3_CCP4IP_LENGTH | none | 0x1 |
_IPR3_CCP4IP_MASK | none | 0x2 |
_IPR3_CCP5IP_POSN | none | 0x2 |
_IPR3_CCP5IP_POSITION | none | 0x2 |
_IPR3_CCP5IP_SIZE | none | 0x1 |
_IPR3_CCP5IP_LENGTH | none | 0x1 |
_IPR3_CCP5IP_MASK | none | 0x4 |
_IPR3_TMR4IP_POSN | none | 0x3 |
_IPR3_TMR4IP_POSITION | none | 0x3 |
_IPR3_TMR4IP_SIZE | none | 0x1 |
_IPR3_TMR4IP_LENGTH | none | 0x1 |
_IPR3_TMR4IP_MASK | none | 0x8 |
_IPR3_TX2IP_POSN | none | 0x4 |
_IPR3_TX2IP_POSITION | none | 0x4 |
_IPR3_TX2IP_SIZE | none | 0x1 |
_IPR3_TX2IP_LENGTH | none | 0x1 |
_IPR3_TX2IP_MASK | none | 0x10 |
_IPR3_RC2IP_POSN | none | 0x5 |
_IPR3_RC2IP_POSITION | none | 0x5 |
_IPR3_RC2IP_SIZE | none | 0x1 |
_IPR3_RC2IP_LENGTH | none | 0x1 |
_IPR3_RC2IP_MASK | none | 0x20 |
_IPR3_RXBNIP_POSN | none | 0x1 |
_IPR3_RXBNIP_POSITION | none | 0x1 |
_IPR3_RXBNIP_SIZE | none | 0x1 |
_IPR3_RXBNIP_LENGTH | none | 0x1 |
_IPR3_RXBNIP_MASK | none | 0x2 |
_IPR3_TXBNIP_POSN | none | 0x4 |
_IPR3_TXBNIP_POSITION | none | 0x4 |
_IPR3_TXBNIP_SIZE | none | 0x1 |
_IPR3_TXBNIP_LENGTH | none | 0x1 |
_IPR3_TXBNIP_MASK | none | 0x10 |
EECON1 | none | <\077435>EECON1 |
EECON1 | none | <\077435>EECON1 |
_EECON1_RD_POSN | none | 0x0 |
_EECON1_RD_POSITION | none | 0x0 |
_EECON1_RD_SIZE | none | 0x1 |
_EECON1_RD_LENGTH | none | 0x1 |
_EECON1_RD_MASK | none | 0x1 |
_EECON1_WR_POSN | none | 0x1 |
_EECON1_WR_POSITION | none | 0x1 |
_EECON1_WR_SIZE | none | 0x1 |
_EECON1_WR_LENGTH | none | 0x1 |
_EECON1_WR_MASK | none | 0x2 |
_EECON1_WREN_POSN | none | 0x2 |
_EECON1_WREN_POSITION | none | 0x2 |
_EECON1_WREN_SIZE | none | 0x1 |
_EECON1_WREN_LENGTH | none | 0x1 |
_EECON1_WREN_MASK | none | 0x4 |
_EECON1_WRERR_POSN | none | 0x3 |
_EECON1_WRERR_POSITION | none | 0x3 |
_EECON1_WRERR_SIZE | none | 0x1 |
_EECON1_WRERR_LENGTH | none | 0x1 |
_EECON1_WRERR_MASK | none | 0x8 |
_EECON1_FREE_POSN | none | 0x4 |
_EECON1_FREE_POSITION | none | 0x4 |
_EECON1_FREE_SIZE | none | 0x1 |
_EECON1_FREE_LENGTH | none | 0x1 |
_EECON1_FREE_MASK | none | 0x10 |
_EECON1_CFGS_POSN | none | 0x6 |
_EECON1_CFGS_POSITION | none | 0x6 |
_EECON1_CFGS_SIZE | none | 0x1 |
_EECON1_CFGS_LENGTH | none | 0x1 |
_EECON1_CFGS_MASK | none | 0x40 |
_EECON1_EEPGD_POSN | none | 0x7 |
_EECON1_EEPGD_POSITION | none | 0x7 |
_EECON1_EEPGD_SIZE | none | 0x1 |
_EECON1_EEPGD_LENGTH | none | 0x1 |
_EECON1_EEPGD_MASK | none | 0x80 |
_EECON1_EEFS_POSN | none | 0x6 |
_EECON1_EEFS_POSITION | none | 0x6 |
_EECON1_EEFS_SIZE | none | 0x1 |
_EECON1_EEFS_LENGTH | none | 0x1 |
_EECON1_EEFS_MASK | none | 0x40 |
EECON2 | none | <\077435>EECON2 |
EECON2 | none | <\077435>EECON2 |
EEDATA | none | <\077435>EEDATA |
EEDATA | none | <\077435>EEDATA |
EEADR | none | <\077435>EEADR |
EEADR | none | <\077435>EEADR |
EEADRH | none | <\077435>EEADRH |
EEADRH | none | <\077435>EEADRH |
RCSTA1 | none | <\077435>RCSTA1 |
RCSTA1 | none | <\077435>RCSTA1 |
_RCSTA1_RX9D_POSN | none | 0x0 |
_RCSTA1_RX9D_POSITION | none | 0x0 |
_RCSTA1_RX9D_SIZE | none | 0x1 |
_RCSTA1_RX9D_LENGTH | none | 0x1 |
_RCSTA1_RX9D_MASK | none | 0x1 |
_RCSTA1_OERR_POSN | none | 0x1 |
_RCSTA1_OERR_POSITION | none | 0x1 |
_RCSTA1_OERR_SIZE | none | 0x1 |
_RCSTA1_OERR_LENGTH | none | 0x1 |
_RCSTA1_OERR_MASK | none | 0x2 |
_RCSTA1_FERR_POSN | none | 0x2 |
_RCSTA1_FERR_POSITION | none | 0x2 |
_RCSTA1_FERR_SIZE | none | 0x1 |
_RCSTA1_FERR_LENGTH | none | 0x1 |
_RCSTA1_FERR_MASK | none | 0x4 |
_RCSTA1_ADDEN_POSN | none | 0x3 |
_RCSTA1_ADDEN_POSITION | none | 0x3 |
_RCSTA1_ADDEN_SIZE | none | 0x1 |
_RCSTA1_ADDEN_LENGTH | none | 0x1 |
_RCSTA1_ADDEN_MASK | none | 0x8 |
_RCSTA1_CREN_POSN | none | 0x4 |
_RCSTA1_CREN_POSITION | none | 0x4 |
_RCSTA1_CREN_SIZE | none | 0x1 |
_RCSTA1_CREN_LENGTH | none | 0x1 |
_RCSTA1_CREN_MASK | none | 0x10 |
_RCSTA1_SREN_POSN | none | 0x5 |
_RCSTA1_SREN_POSITION | none | 0x5 |
_RCSTA1_SREN_SIZE | none | 0x1 |
_RCSTA1_SREN_LENGTH | none | 0x1 |
_RCSTA1_SREN_MASK | none | 0x20 |
_RCSTA1_RX9_POSN | none | 0x6 |
_RCSTA1_RX9_POSITION | none | 0x6 |
_RCSTA1_RX9_SIZE | none | 0x1 |
_RCSTA1_RX9_LENGTH | none | 0x1 |
_RCSTA1_RX9_MASK | none | 0x40 |
_RCSTA1_SPEN_POSN | none | 0x7 |
_RCSTA1_SPEN_POSITION | none | 0x7 |
_RCSTA1_SPEN_SIZE | none | 0x1 |
_RCSTA1_SPEN_LENGTH | none | 0x1 |
_RCSTA1_SPEN_MASK | none | 0x80 |
_RCSTA1_RCD8_POSN | none | 0x0 |
_RCSTA1_RCD8_POSITION | none | 0x0 |
_RCSTA1_RCD8_SIZE | none | 0x1 |
_RCSTA1_RCD8_LENGTH | none | 0x1 |
_RCSTA1_RCD8_MASK | none | 0x1 |
_RCSTA1_ADEN_POSN | none | 0x3 |
_RCSTA1_ADEN_POSITION | none | 0x3 |
_RCSTA1_ADEN_SIZE | none | 0x1 |
_RCSTA1_ADEN_LENGTH | none | 0x1 |
_RCSTA1_ADEN_MASK | none | 0x8 |
_RCSTA1_RC9_POSN | none | 0x6 |
_RCSTA1_RC9_POSITION | none | 0x6 |
_RCSTA1_RC9_SIZE | none | 0x1 |
_RCSTA1_RC9_LENGTH | none | 0x1 |
_RCSTA1_RC9_MASK | none | 0x40 |
_RCSTA1_NOT_RC8_POSN | none | 0x6 |
_RCSTA1_NOT_RC8_POSITION | none | 0x6 |
_RCSTA1_NOT_RC8_SIZE | none | 0x1 |
_RCSTA1_NOT_RC8_LENGTH | none | 0x1 |
_RCSTA1_NOT_RC8_MASK | none | 0x40 |
_RCSTA1_nRC8_POSN | none | 0x6 |
_RCSTA1_nRC8_POSITION | none | 0x6 |
_RCSTA1_nRC8_SIZE | none | 0x1 |
_RCSTA1_nRC8_LENGTH | none | 0x1 |
_RCSTA1_nRC8_MASK | none | 0x40 |
_RCSTA1_RC8_9_POSN | none | 0x6 |
_RCSTA1_RC8_9_POSITION | none | 0x6 |
_RCSTA1_RC8_9_SIZE | none | 0x1 |
_RCSTA1_RC8_9_LENGTH | none | 0x1 |
_RCSTA1_RC8_9_MASK | none | 0x40 |
_RCSTA1_RX9D1_POSN | none | 0x0 |
_RCSTA1_RX9D1_POSITION | none | 0x0 |
_RCSTA1_RX9D1_SIZE | none | 0x1 |
_RCSTA1_RX9D1_LENGTH | none | 0x1 |
_RCSTA1_RX9D1_MASK | none | 0x1 |
_RCSTA1_OERR1_POSN | none | 0x1 |
_RCSTA1_OERR1_POSITION | none | 0x1 |
_RCSTA1_OERR1_SIZE | none | 0x1 |
_RCSTA1_OERR1_LENGTH | none | 0x1 |
_RCSTA1_OERR1_MASK | none | 0x2 |
_RCSTA1_FERR1_POSN | none | 0x2 |
_RCSTA1_FERR1_POSITION | none | 0x2 |
_RCSTA1_FERR1_SIZE | none | 0x1 |
_RCSTA1_FERR1_LENGTH | none | 0x1 |
_RCSTA1_FERR1_MASK | none | 0x4 |
_RCSTA1_ADDEN1_POSN | none | 0x3 |
_RCSTA1_ADDEN1_POSITION | none | 0x3 |
_RCSTA1_ADDEN1_SIZE | none | 0x1 |
_RCSTA1_ADDEN1_LENGTH | none | 0x1 |
_RCSTA1_ADDEN1_MASK | none | 0x8 |
_RCSTA1_CREN1_POSN | none | 0x4 |
_RCSTA1_CREN1_POSITION | none | 0x4 |
_RCSTA1_CREN1_SIZE | none | 0x1 |
_RCSTA1_CREN1_LENGTH | none | 0x1 |
_RCSTA1_CREN1_MASK | none | 0x10 |
_RCSTA1_SREN1_POSN | none | 0x5 |
_RCSTA1_SREN1_POSITION | none | 0x5 |
_RCSTA1_SREN1_SIZE | none | 0x1 |
_RCSTA1_SREN1_LENGTH | none | 0x1 |
_RCSTA1_SREN1_MASK | none | 0x20 |
_RCSTA1_RX91_POSN | none | 0x6 |
_RCSTA1_RX91_POSITION | none | 0x6 |
_RCSTA1_RX91_SIZE | none | 0x1 |
_RCSTA1_RX91_LENGTH | none | 0x1 |
_RCSTA1_RX91_MASK | none | 0x40 |
_RCSTA1_SPEN1_POSN | none | 0x7 |
_RCSTA1_SPEN1_POSITION | none | 0x7 |
_RCSTA1_SPEN1_SIZE | none | 0x1 |
_RCSTA1_SPEN1_LENGTH | none | 0x1 |
_RCSTA1_SPEN1_MASK | none | 0x80 |
_RCSTA1_SRENA_POSN | none | 0x5 |
_RCSTA1_SRENA_POSITION | none | 0x5 |
_RCSTA1_SRENA_SIZE | none | 0x1 |
_RCSTA1_SRENA_LENGTH | none | 0x1 |
_RCSTA1_SRENA_MASK | none | 0x20 |
_RCSTA_RX9D_POSN | none | 0x0 |
_RCSTA_RX9D_POSITION | none | 0x0 |
_RCSTA_RX9D_SIZE | none | 0x1 |
_RCSTA_RX9D_LENGTH | none | 0x1 |
_RCSTA_RX9D_MASK | none | 0x1 |
_RCSTA_OERR_POSN | none | 0x1 |
_RCSTA_OERR_POSITION | none | 0x1 |
_RCSTA_OERR_SIZE | none | 0x1 |
_RCSTA_OERR_LENGTH | none | 0x1 |
_RCSTA_OERR_MASK | none | 0x2 |
_RCSTA_FERR_POSN | none | 0x2 |
_RCSTA_FERR_POSITION | none | 0x2 |
_RCSTA_FERR_SIZE | none | 0x1 |
_RCSTA_FERR_LENGTH | none | 0x1 |
_RCSTA_FERR_MASK | none | 0x4 |
_RCSTA_ADDEN_POSN | none | 0x3 |
_RCSTA_ADDEN_POSITION | none | 0x3 |
_RCSTA_ADDEN_SIZE | none | 0x1 |
_RCSTA_ADDEN_LENGTH | none | 0x1 |
_RCSTA_ADDEN_MASK | none | 0x8 |
_RCSTA_CREN_POSN | none | 0x4 |
_RCSTA_CREN_POSITION | none | 0x4 |
_RCSTA_CREN_SIZE | none | 0x1 |
_RCSTA_CREN_LENGTH | none | 0x1 |
_RCSTA_CREN_MASK | none | 0x10 |
_RCSTA_SREN_POSN | none | 0x5 |
_RCSTA_SREN_POSITION | none | 0x5 |
_RCSTA_SREN_SIZE | none | 0x1 |
_RCSTA_SREN_LENGTH | none | 0x1 |
_RCSTA_SREN_MASK | none | 0x20 |
_RCSTA_RX9_POSN | none | 0x6 |
_RCSTA_RX9_POSITION | none | 0x6 |
_RCSTA_RX9_SIZE | none | 0x1 |
_RCSTA_RX9_LENGTH | none | 0x1 |
_RCSTA_RX9_MASK | none | 0x40 |
_RCSTA_SPEN_POSN | none | 0x7 |
_RCSTA_SPEN_POSITION | none | 0x7 |
_RCSTA_SPEN_SIZE | none | 0x1 |
_RCSTA_SPEN_LENGTH | none | 0x1 |
_RCSTA_SPEN_MASK | none | 0x80 |
_RCSTA_RCD8_POSN | none | 0x0 |
_RCSTA_RCD8_POSITION | none | 0x0 |
_RCSTA_RCD8_SIZE | none | 0x1 |
_RCSTA_RCD8_LENGTH | none | 0x1 |
_RCSTA_RCD8_MASK | none | 0x1 |
_RCSTA_ADEN_POSN | none | 0x3 |
_RCSTA_ADEN_POSITION | none | 0x3 |
_RCSTA_ADEN_SIZE | none | 0x1 |
_RCSTA_ADEN_LENGTH | none | 0x1 |
_RCSTA_ADEN_MASK | none | 0x8 |
_RCSTA_RC9_POSN | none | 0x6 |
_RCSTA_RC9_POSITION | none | 0x6 |
_RCSTA_RC9_SIZE | none | 0x1 |
_RCSTA_RC9_LENGTH | none | 0x1 |
_RCSTA_RC9_MASK | none | 0x40 |
_RCSTA_NOT_RC8_POSN | none | 0x6 |
_RCSTA_NOT_RC8_POSITION | none | 0x6 |
_RCSTA_NOT_RC8_SIZE | none | 0x1 |
_RCSTA_NOT_RC8_LENGTH | none | 0x1 |
_RCSTA_NOT_RC8_MASK | none | 0x40 |
_RCSTA_nRC8_POSN | none | 0x6 |
_RCSTA_nRC8_POSITION | none | 0x6 |
_RCSTA_nRC8_SIZE | none | 0x1 |
_RCSTA_nRC8_LENGTH | none | 0x1 |
_RCSTA_nRC8_MASK | none | 0x40 |
_RCSTA_RC8_9_POSN | none | 0x6 |
_RCSTA_RC8_9_POSITION | none | 0x6 |
_RCSTA_RC8_9_SIZE | none | 0x1 |
_RCSTA_RC8_9_LENGTH | none | 0x1 |
_RCSTA_RC8_9_MASK | none | 0x40 |
_RCSTA_RX9D1_POSN | none | 0x0 |
_RCSTA_RX9D1_POSITION | none | 0x0 |
_RCSTA_RX9D1_SIZE | none | 0x1 |
_RCSTA_RX9D1_LENGTH | none | 0x1 |
_RCSTA_RX9D1_MASK | none | 0x1 |
_RCSTA_OERR1_POSN | none | 0x1 |
_RCSTA_OERR1_POSITION | none | 0x1 |
_RCSTA_OERR1_SIZE | none | 0x1 |
_RCSTA_OERR1_LENGTH | none | 0x1 |
_RCSTA_OERR1_MASK | none | 0x2 |
_RCSTA_FERR1_POSN | none | 0x2 |
_RCSTA_FERR1_POSITION | none | 0x2 |
_RCSTA_FERR1_SIZE | none | 0x1 |
_RCSTA_FERR1_LENGTH | none | 0x1 |
_RCSTA_FERR1_MASK | none | 0x4 |
_RCSTA_ADDEN1_POSN | none | 0x3 |
_RCSTA_ADDEN1_POSITION | none | 0x3 |
_RCSTA_ADDEN1_SIZE | none | 0x1 |
_RCSTA_ADDEN1_LENGTH | none | 0x1 |
_RCSTA_ADDEN1_MASK | none | 0x8 |
_RCSTA_CREN1_POSN | none | 0x4 |
_RCSTA_CREN1_POSITION | none | 0x4 |
_RCSTA_CREN1_SIZE | none | 0x1 |
_RCSTA_CREN1_LENGTH | none | 0x1 |
_RCSTA_CREN1_MASK | none | 0x10 |
_RCSTA_SREN1_POSN | none | 0x5 |
_RCSTA_SREN1_POSITION | none | 0x5 |
_RCSTA_SREN1_SIZE | none | 0x1 |
_RCSTA_SREN1_LENGTH | none | 0x1 |
_RCSTA_SREN1_MASK | none | 0x20 |
_RCSTA_RX91_POSN | none | 0x6 |
_RCSTA_RX91_POSITION | none | 0x6 |
_RCSTA_RX91_SIZE | none | 0x1 |
_RCSTA_RX91_LENGTH | none | 0x1 |
_RCSTA_RX91_MASK | none | 0x40 |
_RCSTA_SPEN1_POSN | none | 0x7 |
_RCSTA_SPEN1_POSITION | none | 0x7 |
_RCSTA_SPEN1_SIZE | none | 0x1 |
_RCSTA_SPEN1_LENGTH | none | 0x1 |
_RCSTA_SPEN1_MASK | none | 0x80 |
_RCSTA_SRENA_POSN | none | 0x5 |
_RCSTA_SRENA_POSITION | none | 0x5 |
_RCSTA_SRENA_SIZE | none | 0x1 |
_RCSTA_SRENA_LENGTH | none | 0x1 |
_RCSTA_SRENA_MASK | none | 0x20 |
TXSTA1 | none | <\077435>TXSTA1 |
TXSTA1 | none | <\077435>TXSTA1 |
_TXSTA1_TX9D_POSN | none | 0x0 |
_TXSTA1_TX9D_POSITION | none | 0x0 |
_TXSTA1_TX9D_SIZE | none | 0x1 |
_TXSTA1_TX9D_LENGTH | none | 0x1 |
_TXSTA1_TX9D_MASK | none | 0x1 |
_TXSTA1_TRMT_POSN | none | 0x1 |
_TXSTA1_TRMT_POSITION | none | 0x1 |
_TXSTA1_TRMT_SIZE | none | 0x1 |
_TXSTA1_TRMT_LENGTH | none | 0x1 |
_TXSTA1_TRMT_MASK | none | 0x2 |
_TXSTA1_BRGH_POSN | none | 0x2 |
_TXSTA1_BRGH_POSITION | none | 0x2 |
_TXSTA1_BRGH_SIZE | none | 0x1 |
_TXSTA1_BRGH_LENGTH | none | 0x1 |
_TXSTA1_BRGH_MASK | none | 0x4 |
_TXSTA1_SYNC_POSN | none | 0x4 |
_TXSTA1_SYNC_POSITION | none | 0x4 |
_TXSTA1_SYNC_SIZE | none | 0x1 |
_TXSTA1_SYNC_LENGTH | none | 0x1 |
_TXSTA1_SYNC_MASK | none | 0x10 |
_TXSTA1_TXEN_POSN | none | 0x5 |
_TXSTA1_TXEN_POSITION | none | 0x5 |
_TXSTA1_TXEN_SIZE | none | 0x1 |
_TXSTA1_TXEN_LENGTH | none | 0x1 |
_TXSTA1_TXEN_MASK | none | 0x20 |
_TXSTA1_TX9_POSN | none | 0x6 |
_TXSTA1_TX9_POSITION | none | 0x6 |
_TXSTA1_TX9_SIZE | none | 0x1 |
_TXSTA1_TX9_LENGTH | none | 0x1 |
_TXSTA1_TX9_MASK | none | 0x40 |
_TXSTA1_CSRC_POSN | none | 0x7 |
_TXSTA1_CSRC_POSITION | none | 0x7 |
_TXSTA1_CSRC_SIZE | none | 0x1 |
_TXSTA1_CSRC_LENGTH | none | 0x1 |
_TXSTA1_CSRC_MASK | none | 0x80 |
_TXSTA1_TXD8_POSN | none | 0x0 |
_TXSTA1_TXD8_POSITION | none | 0x0 |
_TXSTA1_TXD8_SIZE | none | 0x1 |
_TXSTA1_TXD8_LENGTH | none | 0x1 |
_TXSTA1_TXD8_MASK | none | 0x1 |
_TXSTA1_TX8_9_POSN | none | 0x6 |
_TXSTA1_TX8_9_POSITION | none | 0x6 |
_TXSTA1_TX8_9_SIZE | none | 0x1 |
_TXSTA1_TX8_9_LENGTH | none | 0x1 |
_TXSTA1_TX8_9_MASK | none | 0x40 |
_TXSTA1_NOT_TX8_POSN | none | 0x6 |
_TXSTA1_NOT_TX8_POSITION | none | 0x6 |
_TXSTA1_NOT_TX8_SIZE | none | 0x1 |
_TXSTA1_NOT_TX8_LENGTH | none | 0x1 |
_TXSTA1_NOT_TX8_MASK | none | 0x40 |
_TXSTA1_nTX8_POSN | none | 0x6 |
_TXSTA1_nTX8_POSITION | none | 0x6 |
_TXSTA1_nTX8_SIZE | none | 0x1 |
_TXSTA1_nTX8_LENGTH | none | 0x1 |
_TXSTA1_nTX8_MASK | none | 0x40 |
_TXSTA1_TX9D1_POSN | none | 0x0 |
_TXSTA1_TX9D1_POSITION | none | 0x0 |
_TXSTA1_TX9D1_SIZE | none | 0x1 |
_TXSTA1_TX9D1_LENGTH | none | 0x1 |
_TXSTA1_TX9D1_MASK | none | 0x1 |
_TXSTA1_TRMT1_POSN | none | 0x1 |
_TXSTA1_TRMT1_POSITION | none | 0x1 |
_TXSTA1_TRMT1_SIZE | none | 0x1 |
_TXSTA1_TRMT1_LENGTH | none | 0x1 |
_TXSTA1_TRMT1_MASK | none | 0x2 |
_TXSTA1_BRGH1_POSN | none | 0x2 |
_TXSTA1_BRGH1_POSITION | none | 0x2 |
_TXSTA1_BRGH1_SIZE | none | 0x1 |
_TXSTA1_BRGH1_LENGTH | none | 0x1 |
_TXSTA1_BRGH1_MASK | none | 0x4 |
_TXSTA1_SENDB1_POSN | none | 0x3 |
_TXSTA1_SENDB1_POSITION | none | 0x3 |
_TXSTA1_SENDB1_SIZE | none | 0x1 |
_TXSTA1_SENDB1_LENGTH | none | 0x1 |
_TXSTA1_SENDB1_MASK | none | 0x8 |
_TXSTA1_SYNC1_POSN | none | 0x4 |
_TXSTA1_SYNC1_POSITION | none | 0x4 |
_TXSTA1_SYNC1_SIZE | none | 0x1 |
_TXSTA1_SYNC1_LENGTH | none | 0x1 |
_TXSTA1_SYNC1_MASK | none | 0x10 |
_TXSTA1_TXEN1_POSN | none | 0x5 |
_TXSTA1_TXEN1_POSITION | none | 0x5 |
_TXSTA1_TXEN1_SIZE | none | 0x1 |
_TXSTA1_TXEN1_LENGTH | none | 0x1 |
_TXSTA1_TXEN1_MASK | none | 0x20 |
_TXSTA1_TX91_POSN | none | 0x6 |
_TXSTA1_TX91_POSITION | none | 0x6 |
_TXSTA1_TX91_SIZE | none | 0x1 |
_TXSTA1_TX91_LENGTH | none | 0x1 |
_TXSTA1_TX91_MASK | none | 0x40 |
_TXSTA1_CSRC1_POSN | none | 0x7 |
_TXSTA1_CSRC1_POSITION | none | 0x7 |
_TXSTA1_CSRC1_SIZE | none | 0x1 |
_TXSTA1_CSRC1_LENGTH | none | 0x1 |
_TXSTA1_CSRC1_MASK | none | 0x80 |
_TXSTA1_SENDB_POSN | none | 0x3 |
_TXSTA1_SENDB_POSITION | none | 0x3 |
_TXSTA1_SENDB_SIZE | none | 0x1 |
_TXSTA1_SENDB_LENGTH | none | 0x1 |
_TXSTA1_SENDB_MASK | none | 0x8 |
_TXSTA_TX9D_POSN | none | 0x0 |
_TXSTA_TX9D_POSITION | none | 0x0 |
_TXSTA_TX9D_SIZE | none | 0x1 |
_TXSTA_TX9D_LENGTH | none | 0x1 |
_TXSTA_TX9D_MASK | none | 0x1 |
_TXSTA_TRMT_POSN | none | 0x1 |
_TXSTA_TRMT_POSITION | none | 0x1 |
_TXSTA_TRMT_SIZE | none | 0x1 |
_TXSTA_TRMT_LENGTH | none | 0x1 |
_TXSTA_TRMT_MASK | none | 0x2 |
_TXSTA_BRGH_POSN | none | 0x2 |
_TXSTA_BRGH_POSITION | none | 0x2 |
_TXSTA_BRGH_SIZE | none | 0x1 |
_TXSTA_BRGH_LENGTH | none | 0x1 |
_TXSTA_BRGH_MASK | none | 0x4 |
_TXSTA_SYNC_POSN | none | 0x4 |
_TXSTA_SYNC_POSITION | none | 0x4 |
_TXSTA_SYNC_SIZE | none | 0x1 |
_TXSTA_SYNC_LENGTH | none | 0x1 |
_TXSTA_SYNC_MASK | none | 0x10 |
_TXSTA_TXEN_POSN | none | 0x5 |
_TXSTA_TXEN_POSITION | none | 0x5 |
_TXSTA_TXEN_SIZE | none | 0x1 |
_TXSTA_TXEN_LENGTH | none | 0x1 |
_TXSTA_TXEN_MASK | none | 0x20 |
_TXSTA_TX9_POSN | none | 0x6 |
_TXSTA_TX9_POSITION | none | 0x6 |
_TXSTA_TX9_SIZE | none | 0x1 |
_TXSTA_TX9_LENGTH | none | 0x1 |
_TXSTA_TX9_MASK | none | 0x40 |
_TXSTA_CSRC_POSN | none | 0x7 |
_TXSTA_CSRC_POSITION | none | 0x7 |
_TXSTA_CSRC_SIZE | none | 0x1 |
_TXSTA_CSRC_LENGTH | none | 0x1 |
_TXSTA_CSRC_MASK | none | 0x80 |
_TXSTA_TXD8_POSN | none | 0x0 |
_TXSTA_TXD8_POSITION | none | 0x0 |
_TXSTA_TXD8_SIZE | none | 0x1 |
_TXSTA_TXD8_LENGTH | none | 0x1 |
_TXSTA_TXD8_MASK | none | 0x1 |
_TXSTA_TX8_9_POSN | none | 0x6 |
_TXSTA_TX8_9_POSITION | none | 0x6 |
_TXSTA_TX8_9_SIZE | none | 0x1 |
_TXSTA_TX8_9_LENGTH | none | 0x1 |
_TXSTA_TX8_9_MASK | none | 0x40 |
_TXSTA_NOT_TX8_POSN | none | 0x6 |
_TXSTA_NOT_TX8_POSITION | none | 0x6 |
_TXSTA_NOT_TX8_SIZE | none | 0x1 |
_TXSTA_NOT_TX8_LENGTH | none | 0x1 |
_TXSTA_NOT_TX8_MASK | none | 0x40 |
_TXSTA_nTX8_POSN | none | 0x6 |
_TXSTA_nTX8_POSITION | none | 0x6 |
_TXSTA_nTX8_SIZE | none | 0x1 |
_TXSTA_nTX8_LENGTH | none | 0x1 |
_TXSTA_nTX8_MASK | none | 0x40 |
_TXSTA_TX9D1_POSN | none | 0x0 |
_TXSTA_TX9D1_POSITION | none | 0x0 |
_TXSTA_TX9D1_SIZE | none | 0x1 |
_TXSTA_TX9D1_LENGTH | none | 0x1 |
_TXSTA_TX9D1_MASK | none | 0x1 |
_TXSTA_TRMT1_POSN | none | 0x1 |
_TXSTA_TRMT1_POSITION | none | 0x1 |
_TXSTA_TRMT1_SIZE | none | 0x1 |
_TXSTA_TRMT1_LENGTH | none | 0x1 |
_TXSTA_TRMT1_MASK | none | 0x2 |
_TXSTA_BRGH1_POSN | none | 0x2 |
_TXSTA_BRGH1_POSITION | none | 0x2 |
_TXSTA_BRGH1_SIZE | none | 0x1 |
_TXSTA_BRGH1_LENGTH | none | 0x1 |
_TXSTA_BRGH1_MASK | none | 0x4 |
_TXSTA_SENDB1_POSN | none | 0x3 |
_TXSTA_SENDB1_POSITION | none | 0x3 |
_TXSTA_SENDB1_SIZE | none | 0x1 |
_TXSTA_SENDB1_LENGTH | none | 0x1 |
_TXSTA_SENDB1_MASK | none | 0x8 |
_TXSTA_SYNC1_POSN | none | 0x4 |
_TXSTA_SYNC1_POSITION | none | 0x4 |
_TXSTA_SYNC1_SIZE | none | 0x1 |
_TXSTA_SYNC1_LENGTH | none | 0x1 |
_TXSTA_SYNC1_MASK | none | 0x10 |
_TXSTA_TXEN1_POSN | none | 0x5 |
_TXSTA_TXEN1_POSITION | none | 0x5 |
_TXSTA_TXEN1_SIZE | none | 0x1 |
_TXSTA_TXEN1_LENGTH | none | 0x1 |
_TXSTA_TXEN1_MASK | none | 0x20 |
_TXSTA_TX91_POSN | none | 0x6 |
_TXSTA_TX91_POSITION | none | 0x6 |
_TXSTA_TX91_SIZE | none | 0x1 |
_TXSTA_TX91_LENGTH | none | 0x1 |
_TXSTA_TX91_MASK | none | 0x40 |
_TXSTA_CSRC1_POSN | none | 0x7 |
_TXSTA_CSRC1_POSITION | none | 0x7 |
_TXSTA_CSRC1_SIZE | none | 0x1 |
_TXSTA_CSRC1_LENGTH | none | 0x1 |
_TXSTA_CSRC1_MASK | none | 0x80 |
_TXSTA_SENDB_POSN | none | 0x3 |
_TXSTA_SENDB_POSITION | none | 0x3 |
_TXSTA_SENDB_SIZE | none | 0x1 |
_TXSTA_SENDB_LENGTH | none | 0x1 |
_TXSTA_SENDB_MASK | none | 0x8 |
TXREG1 | none | <\077435>TXREG1 |
TXREG1 | none | <\077435>TXREG1 |
RCREG1 | none | <\077435>RCREG1 |
RCREG1 | none | <\077435>RCREG1 |
SPBRG1 | none | <\077435>SPBRG1 |
SPBRG1 | none | <\077435>SPBRG1 |
PSPCON | none | <\077435>PSPCON |
PSPCON | none | <\077435>PSPCON |
_PSPCON_PSPMODE_POSN | none | 0x4 |
_PSPCON_PSPMODE_POSITION | none | 0x4 |
_PSPCON_PSPMODE_SIZE | none | 0x1 |
_PSPCON_PSPMODE_LENGTH | none | 0x1 |
_PSPCON_PSPMODE_MASK | none | 0x10 |
_PSPCON_IBOV_POSN | none | 0x5 |
_PSPCON_IBOV_POSITION | none | 0x5 |
_PSPCON_IBOV_SIZE | none | 0x1 |
_PSPCON_IBOV_LENGTH | none | 0x1 |
_PSPCON_IBOV_MASK | none | 0x20 |
_PSPCON_OBF_POSN | none | 0x6 |
_PSPCON_OBF_POSITION | none | 0x6 |
_PSPCON_OBF_SIZE | none | 0x1 |
_PSPCON_OBF_LENGTH | none | 0x1 |
_PSPCON_OBF_MASK | none | 0x40 |
_PSPCON_IBF_POSN | none | 0x7 |
_PSPCON_IBF_POSITION | none | 0x7 |
_PSPCON_IBF_SIZE | none | 0x1 |
_PSPCON_IBF_LENGTH | none | 0x1 |
_PSPCON_IBF_MASK | none | 0x80 |
T3CON | none | <\077435>T3CON |
T3CON | none | <\077435>T3CON |
_T3CON_NOT_T3SYNC_POSN | none | 0x2 |
_T3CON_NOT_T3SYNC_POSITION | none | 0x2 |
_T3CON_NOT_T3SYNC_SIZE | none | 0x1 |
_T3CON_NOT_T3SYNC_LENGTH | none | 0x1 |
_T3CON_NOT_T3SYNC_MASK | none | 0x4 |
_T3CON_TMR3ON_POSN | none | 0x0 |
_T3CON_TMR3ON_POSITION | none | 0x0 |
_T3CON_TMR3ON_SIZE | none | 0x1 |
_T3CON_TMR3ON_LENGTH | none | 0x1 |
_T3CON_TMR3ON_MASK | none | 0x1 |
_T3CON_TMR3CS_POSN | none | 0x1 |
_T3CON_TMR3CS_POSITION | none | 0x1 |
_T3CON_TMR3CS_SIZE | none | 0x1 |
_T3CON_TMR3CS_LENGTH | none | 0x1 |
_T3CON_TMR3CS_MASK | none | 0x2 |
_T3CON_nT3SYNC_POSN | none | 0x2 |
_T3CON_nT3SYNC_POSITION | none | 0x2 |
_T3CON_nT3SYNC_SIZE | none | 0x1 |
_T3CON_nT3SYNC_LENGTH | none | 0x1 |
_T3CON_nT3SYNC_MASK | none | 0x4 |
_T3CON_T3CCP1_POSN | none | 0x3 |
_T3CON_T3CCP1_POSITION | none | 0x3 |
_T3CON_T3CCP1_SIZE | none | 0x1 |
_T3CON_T3CCP1_LENGTH | none | 0x1 |
_T3CON_T3CCP1_MASK | none | 0x8 |
_T3CON_T3CKPS_POSN | none | 0x4 |
_T3CON_T3CKPS_POSITION | none | 0x4 |
_T3CON_T3CKPS_SIZE | none | 0x2 |
_T3CON_T3CKPS_LENGTH | none | 0x2 |
_T3CON_T3CKPS_MASK | none | 0x30 |
_T3CON_T3CCP2_POSN | none | 0x6 |
_T3CON_T3CCP2_POSITION | none | 0x6 |
_T3CON_T3CCP2_SIZE | none | 0x1 |
_T3CON_T3CCP2_LENGTH | none | 0x1 |
_T3CON_T3CCP2_MASK | none | 0x40 |
_T3CON_RD16_POSN | none | 0x7 |
_T3CON_RD16_POSITION | none | 0x7 |
_T3CON_RD16_SIZE | none | 0x1 |
_T3CON_RD16_LENGTH | none | 0x1 |
_T3CON_RD16_MASK | none | 0x80 |
_T3CON_T3SYNC_POSN | none | 0x2 |
_T3CON_T3SYNC_POSITION | none | 0x2 |
_T3CON_T3SYNC_SIZE | none | 0x1 |
_T3CON_T3SYNC_LENGTH | none | 0x1 |
_T3CON_T3SYNC_MASK | none | 0x4 |
_T3CON_T3CKPS0_POSN | none | 0x4 |
_T3CON_T3CKPS0_POSITION | none | 0x4 |
_T3CON_T3CKPS0_SIZE | none | 0x1 |
_T3CON_T3CKPS0_LENGTH | none | 0x1 |
_T3CON_T3CKPS0_MASK | none | 0x10 |
_T3CON_T3CKPS1_POSN | none | 0x5 |
_T3CON_T3CKPS1_POSITION | none | 0x5 |
_T3CON_T3CKPS1_SIZE | none | 0x1 |
_T3CON_T3CKPS1_LENGTH | none | 0x1 |
_T3CON_T3CKPS1_MASK | none | 0x20 |
_T3CON_T3INSYNC_POSN | none | 0x2 |
_T3CON_T3INSYNC_POSITION | none | 0x2 |
_T3CON_T3INSYNC_SIZE | none | 0x1 |
_T3CON_T3INSYNC_LENGTH | none | 0x1 |
_T3CON_T3INSYNC_MASK | none | 0x4 |
_T3CON_T3NSYNC_POSN | none | 0x2 |
_T3CON_T3NSYNC_POSITION | none | 0x2 |
_T3CON_T3NSYNC_SIZE | none | 0x1 |
_T3CON_T3NSYNC_LENGTH | none | 0x1 |
_T3CON_T3NSYNC_MASK | none | 0x4 |
_T3CON_SOSCEN3_POSN | none | 0x3 |
_T3CON_SOSCEN3_POSITION | none | 0x3 |
_T3CON_SOSCEN3_SIZE | none | 0x1 |
_T3CON_SOSCEN3_LENGTH | none | 0x1 |
_T3CON_SOSCEN3_MASK | none | 0x8 |
_T3CON_RD163_POSN | none | 0x7 |
_T3CON_RD163_POSITION | none | 0x7 |
_T3CON_RD163_SIZE | none | 0x1 |
_T3CON_RD163_LENGTH | none | 0x1 |
_T3CON_RD163_MASK | none | 0x80 |
_T3CON_T3RD16_POSN | none | 0x7 |
_T3CON_T3RD16_POSITION | none | 0x7 |
_T3CON_T3RD16_SIZE | none | 0x1 |
_T3CON_T3RD16_LENGTH | none | 0x1 |
_T3CON_T3RD16_MASK | none | 0x80 |
TMR3 | none | <\077435>TMR3 |
TMR3 | none | <\077435>TMR3 |
TMR3L | none | <\077435>TMR3L |
TMR3L | none | <\077435>TMR3L |
TMR3H | none | <\077435>TMR3H |
TMR3H | none | <\077435>TMR3H |
CMCON | none | <\077435>CMCON |
CMCON | none | <\077435>CMCON |
_CMCON_CM_POSN | none | 0x0 |
_CMCON_CM_POSITION | none | 0x0 |
_CMCON_CM_SIZE | none | 0x3 |
_CMCON_CM_LENGTH | none | 0x3 |
_CMCON_CM_MASK | none | 0x7 |
_CMCON_CIS_POSN | none | 0x3 |
_CMCON_CIS_POSITION | none | 0x3 |
_CMCON_CIS_SIZE | none | 0x1 |
_CMCON_CIS_LENGTH | none | 0x1 |
_CMCON_CIS_MASK | none | 0x8 |
_CMCON_C1INV_POSN | none | 0x4 |
_CMCON_C1INV_POSITION | none | 0x4 |
_CMCON_C1INV_SIZE | none | 0x1 |
_CMCON_C1INV_LENGTH | none | 0x1 |
_CMCON_C1INV_MASK | none | 0x10 |
_CMCON_C2INV_POSN | none | 0x5 |
_CMCON_C2INV_POSITION | none | 0x5 |
_CMCON_C2INV_SIZE | none | 0x1 |
_CMCON_C2INV_LENGTH | none | 0x1 |
_CMCON_C2INV_MASK | none | 0x20 |
_CMCON_C1OUT_POSN | none | 0x6 |
_CMCON_C1OUT_POSITION | none | 0x6 |
_CMCON_C1OUT_SIZE | none | 0x1 |
_CMCON_C1OUT_LENGTH | none | 0x1 |
_CMCON_C1OUT_MASK | none | 0x40 |
_CMCON_C2OUT_POSN | none | 0x7 |
_CMCON_C2OUT_POSITION | none | 0x7 |
_CMCON_C2OUT_SIZE | none | 0x1 |
_CMCON_C2OUT_LENGTH | none | 0x1 |
_CMCON_C2OUT_MASK | none | 0x80 |
_CMCON_CM0_POSN | none | 0x0 |
_CMCON_CM0_POSITION | none | 0x0 |
_CMCON_CM0_SIZE | none | 0x1 |
_CMCON_CM0_LENGTH | none | 0x1 |
_CMCON_CM0_MASK | none | 0x1 |
_CMCON_CM1_POSN | none | 0x1 |
_CMCON_CM1_POSITION | none | 0x1 |
_CMCON_CM1_SIZE | none | 0x1 |
_CMCON_CM1_LENGTH | none | 0x1 |
_CMCON_CM1_MASK | none | 0x2 |
_CMCON_CM2_POSN | none | 0x2 |
_CMCON_CM2_POSITION | none | 0x2 |
_CMCON_CM2_SIZE | none | 0x1 |
_CMCON_CM2_LENGTH | none | 0x1 |
_CMCON_CM2_MASK | none | 0x4 |
_CMCON_CMEN0_POSN | none | 0x0 |
_CMCON_CMEN0_POSITION | none | 0x0 |
_CMCON_CMEN0_SIZE | none | 0x1 |
_CMCON_CMEN0_LENGTH | none | 0x1 |
_CMCON_CMEN0_MASK | none | 0x1 |
_CMCON_CMEN1_POSN | none | 0x1 |
_CMCON_CMEN1_POSITION | none | 0x1 |
_CMCON_CMEN1_SIZE | none | 0x1 |
_CMCON_CMEN1_LENGTH | none | 0x1 |
_CMCON_CMEN1_MASK | none | 0x2 |
_CMCON_CMEN2_POSN | none | 0x2 |
_CMCON_CMEN2_POSITION | none | 0x2 |
_CMCON_CMEN2_SIZE | none | 0x1 |
_CMCON_CMEN2_LENGTH | none | 0x1 |
_CMCON_CMEN2_MASK | none | 0x4 |
CVRCON | none | <\077435>CVRCON |
CVRCON | none | <\077435>CVRCON |
_CVRCON_CVR_POSN | none | 0x0 |
_CVRCON_CVR_POSITION | none | 0x0 |
_CVRCON_CVR_SIZE | none | 0x4 |
_CVRCON_CVR_LENGTH | none | 0x4 |
_CVRCON_CVR_MASK | none | 0xF |
_CVRCON_CVRSS_POSN | none | 0x4 |
_CVRCON_CVRSS_POSITION | none | 0x4 |
_CVRCON_CVRSS_SIZE | none | 0x1 |
_CVRCON_CVRSS_LENGTH | none | 0x1 |
_CVRCON_CVRSS_MASK | none | 0x10 |
_CVRCON_CVRR_POSN | none | 0x5 |
_CVRCON_CVRR_POSITION | none | 0x5 |
_CVRCON_CVRR_SIZE | none | 0x1 |
_CVRCON_CVRR_LENGTH | none | 0x1 |
_CVRCON_CVRR_MASK | none | 0x20 |
_CVRCON_CVROE_POSN | none | 0x6 |
_CVRCON_CVROE_POSITION | none | 0x6 |
_CVRCON_CVROE_SIZE | none | 0x1 |
_CVRCON_CVROE_LENGTH | none | 0x1 |
_CVRCON_CVROE_MASK | none | 0x40 |
_CVRCON_CVREN_POSN | none | 0x7 |
_CVRCON_CVREN_POSITION | none | 0x7 |
_CVRCON_CVREN_SIZE | none | 0x1 |
_CVRCON_CVREN_LENGTH | none | 0x1 |
_CVRCON_CVREN_MASK | none | 0x80 |
_CVRCON_CVR0_POSN | none | 0x0 |
_CVRCON_CVR0_POSITION | none | 0x0 |
_CVRCON_CVR0_SIZE | none | 0x1 |
_CVRCON_CVR0_LENGTH | none | 0x1 |
_CVRCON_CVR0_MASK | none | 0x1 |
_CVRCON_CVR1_POSN | none | 0x1 |
_CVRCON_CVR1_POSITION | none | 0x1 |
_CVRCON_CVR1_SIZE | none | 0x1 |
_CVRCON_CVR1_LENGTH | none | 0x1 |
_CVRCON_CVR1_MASK | none | 0x2 |
_CVRCON_CVR2_POSN | none | 0x2 |
_CVRCON_CVR2_POSITION | none | 0x2 |
_CVRCON_CVR2_SIZE | none | 0x1 |
_CVRCON_CVR2_LENGTH | none | 0x1 |
_CVRCON_CVR2_MASK | none | 0x4 |
_CVRCON_CVR3_POSN | none | 0x3 |
_CVRCON_CVR3_POSITION | none | 0x3 |
_CVRCON_CVR3_SIZE | none | 0x1 |
_CVRCON_CVR3_LENGTH | none | 0x1 |
_CVRCON_CVR3_MASK | none | 0x8 |
_CVRCON_CVREF_POSN | none | 0x4 |
_CVRCON_CVREF_POSITION | none | 0x4 |
_CVRCON_CVREF_SIZE | none | 0x1 |
_CVRCON_CVREF_LENGTH | none | 0x1 |
_CVRCON_CVREF_MASK | none | 0x10 |
_CVRCON_CVROEN_POSN | none | 0x6 |
_CVRCON_CVROEN_POSITION | none | 0x6 |
_CVRCON_CVROEN_SIZE | none | 0x1 |
_CVRCON_CVROEN_LENGTH | none | 0x1 |
_CVRCON_CVROEN_MASK | none | 0x40 |
CCP3CON | none | <\077435>CCP3CON |
CCP3CON | none | <\077435>CCP3CON |
_CCP3CON_CCP3M_POSN | none | 0x0 |
_CCP3CON_CCP3M_POSITION | none | 0x0 |
_CCP3CON_CCP3M_SIZE | none | 0x4 |
_CCP3CON_CCP3M_LENGTH | none | 0x4 |
_CCP3CON_CCP3M_MASK | none | 0xF |
_CCP3CON_DC3B_POSN | none | 0x4 |
_CCP3CON_DC3B_POSITION | none | 0x4 |
_CCP3CON_DC3B_SIZE | none | 0x2 |
_CCP3CON_DC3B_LENGTH | none | 0x2 |
_CCP3CON_DC3B_MASK | none | 0x30 |
_CCP3CON_CCP3M0_POSN | none | 0x0 |
_CCP3CON_CCP3M0_POSITION | none | 0x0 |
_CCP3CON_CCP3M0_SIZE | none | 0x1 |
_CCP3CON_CCP3M0_LENGTH | none | 0x1 |
_CCP3CON_CCP3M0_MASK | none | 0x1 |
_CCP3CON_CCP3M1_POSN | none | 0x1 |
_CCP3CON_CCP3M1_POSITION | none | 0x1 |
_CCP3CON_CCP3M1_SIZE | none | 0x1 |
_CCP3CON_CCP3M1_LENGTH | none | 0x1 |
_CCP3CON_CCP3M1_MASK | none | 0x2 |
_CCP3CON_CCP3M2_POSN | none | 0x2 |
_CCP3CON_CCP3M2_POSITION | none | 0x2 |
_CCP3CON_CCP3M2_SIZE | none | 0x1 |
_CCP3CON_CCP3M2_LENGTH | none | 0x1 |
_CCP3CON_CCP3M2_MASK | none | 0x4 |
_CCP3CON_CCP3M3_POSN | none | 0x3 |
_CCP3CON_CCP3M3_POSITION | none | 0x3 |
_CCP3CON_CCP3M3_SIZE | none | 0x1 |
_CCP3CON_CCP3M3_LENGTH | none | 0x1 |
_CCP3CON_CCP3M3_MASK | none | 0x8 |
_CCP3CON_DC3B0_POSN | none | 0x4 |
_CCP3CON_DC3B0_POSITION | none | 0x4 |
_CCP3CON_DC3B0_SIZE | none | 0x1 |
_CCP3CON_DC3B0_LENGTH | none | 0x1 |
_CCP3CON_DC3B0_MASK | none | 0x10 |
_CCP3CON_DC3B1_POSN | none | 0x5 |
_CCP3CON_DC3B1_POSITION | none | 0x5 |
_CCP3CON_DC3B1_SIZE | none | 0x1 |
_CCP3CON_DC3B1_LENGTH | none | 0x1 |
_CCP3CON_DC3B1_MASK | none | 0x20 |
_CCP3CON_DCCP3Y_POSN | none | 0x4 |
_CCP3CON_DCCP3Y_POSITION | none | 0x4 |
_CCP3CON_DCCP3Y_SIZE | none | 0x1 |
_CCP3CON_DCCP3Y_LENGTH | none | 0x1 |
_CCP3CON_DCCP3Y_MASK | none | 0x10 |
_CCP3CON_DCCP3X_POSN | none | 0x5 |
_CCP3CON_DCCP3X_POSITION | none | 0x5 |
_CCP3CON_DCCP3X_SIZE | none | 0x1 |
_CCP3CON_DCCP3X_LENGTH | none | 0x1 |
_CCP3CON_DCCP3X_MASK | none | 0x20 |
CCPR3 | none | <\077435>CCPR3 |
CCPR3 | none | <\077435>CCPR3 |
CCPR3L | none | <\077435>CCPR3L |
CCPR3L | none | <\077435>CCPR3L |
CCPR3H | none | <\077435>CCPR3H |
CCPR3H | none | <\077435>CCPR3H |
CCP2CON | none | <\077435>CCP2CON |
CCP2CON | none | <\077435>CCP2CON |
_CCP2CON_CCP2M_POSN | none | 0x0 |
_CCP2CON_CCP2M_POSITION | none | 0x0 |
_CCP2CON_CCP2M_SIZE | none | 0x4 |
_CCP2CON_CCP2M_LENGTH | none | 0x4 |
_CCP2CON_CCP2M_MASK | none | 0xF |
_CCP2CON_DC2B_POSN | none | 0x4 |
_CCP2CON_DC2B_POSITION | none | 0x4 |
_CCP2CON_DC2B_SIZE | none | 0x2 |
_CCP2CON_DC2B_LENGTH | none | 0x2 |
_CCP2CON_DC2B_MASK | none | 0x30 |
_CCP2CON_CCP2M0_POSN | none | 0x0 |
_CCP2CON_CCP2M0_POSITION | none | 0x0 |
_CCP2CON_CCP2M0_SIZE | none | 0x1 |
_CCP2CON_CCP2M0_LENGTH | none | 0x1 |
_CCP2CON_CCP2M0_MASK | none | 0x1 |
_CCP2CON_CCP2M1_POSN | none | 0x1 |
_CCP2CON_CCP2M1_POSITION | none | 0x1 |
_CCP2CON_CCP2M1_SIZE | none | 0x1 |
_CCP2CON_CCP2M1_LENGTH | none | 0x1 |
_CCP2CON_CCP2M1_MASK | none | 0x2 |
_CCP2CON_CCP2M2_POSN | none | 0x2 |
_CCP2CON_CCP2M2_POSITION | none | 0x2 |
_CCP2CON_CCP2M2_SIZE | none | 0x1 |
_CCP2CON_CCP2M2_LENGTH | none | 0x1 |
_CCP2CON_CCP2M2_MASK | none | 0x4 |
_CCP2CON_CCP2M3_POSN | none | 0x3 |
_CCP2CON_CCP2M3_POSITION | none | 0x3 |
_CCP2CON_CCP2M3_SIZE | none | 0x1 |
_CCP2CON_CCP2M3_LENGTH | none | 0x1 |
_CCP2CON_CCP2M3_MASK | none | 0x8 |
_CCP2CON_DC2B0_POSN | none | 0x4 |
_CCP2CON_DC2B0_POSITION | none | 0x4 |
_CCP2CON_DC2B0_SIZE | none | 0x1 |
_CCP2CON_DC2B0_LENGTH | none | 0x1 |
_CCP2CON_DC2B0_MASK | none | 0x10 |
_CCP2CON_DC2B1_POSN | none | 0x5 |
_CCP2CON_DC2B1_POSITION | none | 0x5 |
_CCP2CON_DC2B1_SIZE | none | 0x1 |
_CCP2CON_DC2B1_LENGTH | none | 0x1 |
_CCP2CON_DC2B1_MASK | none | 0x20 |
_CCP2CON_CCP2Y_POSN | none | 0x4 |
_CCP2CON_CCP2Y_POSITION | none | 0x4 |
_CCP2CON_CCP2Y_SIZE | none | 0x1 |
_CCP2CON_CCP2Y_LENGTH | none | 0x1 |
_CCP2CON_CCP2Y_MASK | none | 0x10 |
_CCP2CON_CCP2X_POSN | none | 0x5 |
_CCP2CON_CCP2X_POSITION | none | 0x5 |
_CCP2CON_CCP2X_SIZE | none | 0x1 |
_CCP2CON_CCP2X_LENGTH | none | 0x1 |
_CCP2CON_CCP2X_MASK | none | 0x20 |
_CCP2CON_DCCP2Y_POSN | none | 0x4 |
_CCP2CON_DCCP2Y_POSITION | none | 0x4 |
_CCP2CON_DCCP2Y_SIZE | none | 0x1 |
_CCP2CON_DCCP2Y_LENGTH | none | 0x1 |
_CCP2CON_DCCP2Y_MASK | none | 0x10 |
_CCP2CON_DCCP2X_POSN | none | 0x5 |
_CCP2CON_DCCP2X_POSITION | none | 0x5 |
_CCP2CON_DCCP2X_SIZE | none | 0x1 |
_CCP2CON_DCCP2X_LENGTH | none | 0x1 |
_CCP2CON_DCCP2X_MASK | none | 0x20 |
CCPR2 | none | <\077435>CCPR2 |
CCPR2 | none | <\077435>CCPR2 |
CCPR2L | none | <\077435>CCPR2L |
CCPR2L | none | <\077435>CCPR2L |
CCPR2H | none | <\077435>CCPR2H |
CCPR2H | none | <\077435>CCPR2H |
CCP1CON | none | <\077435>CCP1CON |
CCP1CON | none | <\077435>CCP1CON |
_CCP1CON_CCP1M_POSN | none | 0x0 |
_CCP1CON_CCP1M_POSITION | none | 0x0 |
_CCP1CON_CCP1M_SIZE | none | 0x4 |
_CCP1CON_CCP1M_LENGTH | none | 0x4 |
_CCP1CON_CCP1M_MASK | none | 0xF |
_CCP1CON_DC1B_POSN | none | 0x4 |
_CCP1CON_DC1B_POSITION | none | 0x4 |
_CCP1CON_DC1B_SIZE | none | 0x2 |
_CCP1CON_DC1B_LENGTH | none | 0x2 |
_CCP1CON_DC1B_MASK | none | 0x30 |
_CCP1CON_CCP1M0_POSN | none | 0x0 |
_CCP1CON_CCP1M0_POSITION | none | 0x0 |
_CCP1CON_CCP1M0_SIZE | none | 0x1 |
_CCP1CON_CCP1M0_LENGTH | none | 0x1 |
_CCP1CON_CCP1M0_MASK | none | 0x1 |
_CCP1CON_CCP1M1_POSN | none | 0x1 |
_CCP1CON_CCP1M1_POSITION | none | 0x1 |
_CCP1CON_CCP1M1_SIZE | none | 0x1 |
_CCP1CON_CCP1M1_LENGTH | none | 0x1 |
_CCP1CON_CCP1M1_MASK | none | 0x2 |
_CCP1CON_CCP1M2_POSN | none | 0x2 |
_CCP1CON_CCP1M2_POSITION | none | 0x2 |
_CCP1CON_CCP1M2_SIZE | none | 0x1 |
_CCP1CON_CCP1M2_LENGTH | none | 0x1 |
_CCP1CON_CCP1M2_MASK | none | 0x4 |
_CCP1CON_CCP1M3_POSN | none | 0x3 |
_CCP1CON_CCP1M3_POSITION | none | 0x3 |
_CCP1CON_CCP1M3_SIZE | none | 0x1 |
_CCP1CON_CCP1M3_LENGTH | none | 0x1 |
_CCP1CON_CCP1M3_MASK | none | 0x8 |
_CCP1CON_DC1B0_POSN | none | 0x4 |
_CCP1CON_DC1B0_POSITION | none | 0x4 |
_CCP1CON_DC1B0_SIZE | none | 0x1 |
_CCP1CON_DC1B0_LENGTH | none | 0x1 |
_CCP1CON_DC1B0_MASK | none | 0x10 |
_CCP1CON_DC1B1_POSN | none | 0x5 |
_CCP1CON_DC1B1_POSITION | none | 0x5 |
_CCP1CON_DC1B1_SIZE | none | 0x1 |
_CCP1CON_DC1B1_LENGTH | none | 0x1 |
_CCP1CON_DC1B1_MASK | none | 0x20 |
_CCP1CON_CCP1Y_POSN | none | 0x4 |
_CCP1CON_CCP1Y_POSITION | none | 0x4 |
_CCP1CON_CCP1Y_SIZE | none | 0x1 |
_CCP1CON_CCP1Y_LENGTH | none | 0x1 |
_CCP1CON_CCP1Y_MASK | none | 0x10 |
_CCP1CON_CCP1X_POSN | none | 0x5 |
_CCP1CON_CCP1X_POSITION | none | 0x5 |
_CCP1CON_CCP1X_SIZE | none | 0x1 |
_CCP1CON_CCP1X_LENGTH | none | 0x1 |
_CCP1CON_CCP1X_MASK | none | 0x20 |
_CCP1CON_DCCP1Y_POSN | none | 0x4 |
_CCP1CON_DCCP1Y_POSITION | none | 0x4 |
_CCP1CON_DCCP1Y_SIZE | none | 0x1 |
_CCP1CON_DCCP1Y_LENGTH | none | 0x1 |
_CCP1CON_DCCP1Y_MASK | none | 0x10 |
_CCP1CON_DCCP1X_POSN | none | 0x5 |
_CCP1CON_DCCP1X_POSITION | none | 0x5 |
_CCP1CON_DCCP1X_SIZE | none | 0x1 |
_CCP1CON_DCCP1X_LENGTH | none | 0x1 |
_CCP1CON_DCCP1X_MASK | none | 0x20 |
CCPR1 | none | <\077435>CCPR1 |
CCPR1 | none | <\077435>CCPR1 |
CCPR1L | none | <\077435>CCPR1L |
CCPR1L | none | <\077435>CCPR1L |
CCPR1H | none | <\077435>CCPR1H |
CCPR1H | none | <\077435>CCPR1H |
ADCON2 | none | <\077435>ADCON2 |
ADCON2 | none | <\077435>ADCON2 |
_ADCON2_ADCS_POSN | none | 0x0 |
_ADCON2_ADCS_POSITION | none | 0x0 |
_ADCON2_ADCS_SIZE | none | 0x3 |
_ADCON2_ADCS_LENGTH | none | 0x3 |
_ADCON2_ADCS_MASK | none | 0x7 |
_ADCON2_ADFM_POSN | none | 0x7 |
_ADCON2_ADFM_POSITION | none | 0x7 |
_ADCON2_ADFM_SIZE | none | 0x1 |
_ADCON2_ADFM_LENGTH | none | 0x1 |
_ADCON2_ADFM_MASK | none | 0x80 |
_ADCON2_ADCS0_POSN | none | 0x0 |
_ADCON2_ADCS0_POSITION | none | 0x0 |
_ADCON2_ADCS0_SIZE | none | 0x1 |
_ADCON2_ADCS0_LENGTH | none | 0x1 |
_ADCON2_ADCS0_MASK | none | 0x1 |
_ADCON2_ADCS1_POSN | none | 0x1 |
_ADCON2_ADCS1_POSITION | none | 0x1 |
_ADCON2_ADCS1_SIZE | none | 0x1 |
_ADCON2_ADCS1_LENGTH | none | 0x1 |
_ADCON2_ADCS1_MASK | none | 0x2 |
_ADCON2_ADCS2_POSN | none | 0x2 |
_ADCON2_ADCS2_POSITION | none | 0x2 |
_ADCON2_ADCS2_SIZE | none | 0x1 |
_ADCON2_ADCS2_LENGTH | none | 0x1 |
_ADCON2_ADCS2_MASK | none | 0x4 |
ADCON1 | none | <\077435>ADCON1 |
ADCON1 | none | <\077435>ADCON1 |
_ADCON1_PCFG_POSN | none | 0x0 |
_ADCON1_PCFG_POSITION | none | 0x0 |
_ADCON1_PCFG_SIZE | none | 0x4 |
_ADCON1_PCFG_LENGTH | none | 0x4 |
_ADCON1_PCFG_MASK | none | 0xF |
_ADCON1_VCFG_POSN | none | 0x4 |
_ADCON1_VCFG_POSITION | none | 0x4 |
_ADCON1_VCFG_SIZE | none | 0x2 |
_ADCON1_VCFG_LENGTH | none | 0x2 |
_ADCON1_VCFG_MASK | none | 0x30 |
_ADCON1_PCFG0_POSN | none | 0x0 |
_ADCON1_PCFG0_POSITION | none | 0x0 |
_ADCON1_PCFG0_SIZE | none | 0x1 |
_ADCON1_PCFG0_LENGTH | none | 0x1 |
_ADCON1_PCFG0_MASK | none | 0x1 |
_ADCON1_PCFG1_POSN | none | 0x1 |
_ADCON1_PCFG1_POSITION | none | 0x1 |
_ADCON1_PCFG1_SIZE | none | 0x1 |
_ADCON1_PCFG1_LENGTH | none | 0x1 |
_ADCON1_PCFG1_MASK | none | 0x2 |
_ADCON1_PCFG2_POSN | none | 0x2 |
_ADCON1_PCFG2_POSITION | none | 0x2 |
_ADCON1_PCFG2_SIZE | none | 0x1 |
_ADCON1_PCFG2_LENGTH | none | 0x1 |
_ADCON1_PCFG2_MASK | none | 0x4 |
_ADCON1_PCFG3_POSN | none | 0x3 |
_ADCON1_PCFG3_POSITION | none | 0x3 |
_ADCON1_PCFG3_SIZE | none | 0x1 |
_ADCON1_PCFG3_LENGTH | none | 0x1 |
_ADCON1_PCFG3_MASK | none | 0x8 |
_ADCON1_VCFG0_POSN | none | 0x4 |
_ADCON1_VCFG0_POSITION | none | 0x4 |
_ADCON1_VCFG0_SIZE | none | 0x1 |
_ADCON1_VCFG0_LENGTH | none | 0x1 |
_ADCON1_VCFG0_MASK | none | 0x10 |
_ADCON1_VCFG1_POSN | none | 0x5 |
_ADCON1_VCFG1_POSITION | none | 0x5 |
_ADCON1_VCFG1_SIZE | none | 0x1 |
_ADCON1_VCFG1_LENGTH | none | 0x1 |
_ADCON1_VCFG1_MASK | none | 0x20 |
_ADCON1_CHSN3_POSN | none | 0x3 |
_ADCON1_CHSN3_POSITION | none | 0x3 |
_ADCON1_CHSN3_SIZE | none | 0x1 |
_ADCON1_CHSN3_LENGTH | none | 0x1 |
_ADCON1_CHSN3_MASK | none | 0x8 |
_ADCON1_VCFG01_POSN | none | 0x4 |
_ADCON1_VCFG01_POSITION | none | 0x4 |
_ADCON1_VCFG01_SIZE | none | 0x1 |
_ADCON1_VCFG01_LENGTH | none | 0x1 |
_ADCON1_VCFG01_MASK | none | 0x10 |
_ADCON1_VCFG11_POSN | none | 0x5 |
_ADCON1_VCFG11_POSITION | none | 0x5 |
_ADCON1_VCFG11_SIZE | none | 0x1 |
_ADCON1_VCFG11_LENGTH | none | 0x1 |
_ADCON1_VCFG11_MASK | none | 0x20 |
ADCON0 | none | <\077435>ADCON0 |
ADCON0 | none | <\077435>ADCON0 |
_ADCON0_GO_NOT_DONE_POSN | none | 0x1 |
_ADCON0_GO_NOT_DONE_POSITION | none | 0x1 |
_ADCON0_GO_NOT_DONE_SIZE | none | 0x1 |
_ADCON0_GO_NOT_DONE_LENGTH | none | 0x1 |
_ADCON0_GO_NOT_DONE_MASK | none | 0x2 |
_ADCON0_ADON_POSN | none | 0x0 |
_ADCON0_ADON_POSITION | none | 0x0 |
_ADCON0_ADON_SIZE | none | 0x1 |
_ADCON0_ADON_LENGTH | none | 0x1 |
_ADCON0_ADON_MASK | none | 0x1 |
_ADCON0_GO_nDONE_POSN | none | 0x1 |
_ADCON0_GO_nDONE_POSITION | none | 0x1 |
_ADCON0_GO_nDONE_SIZE | none | 0x1 |
_ADCON0_GO_nDONE_LENGTH | none | 0x1 |
_ADCON0_GO_nDONE_MASK | none | 0x2 |
_ADCON0_CHS_POSN | none | 0x2 |
_ADCON0_CHS_POSITION | none | 0x2 |
_ADCON0_CHS_SIZE | none | 0x4 |
_ADCON0_CHS_LENGTH | none | 0x4 |
_ADCON0_CHS_MASK | none | 0x3C |
_ADCON0_DONE_POSN | none | 0x1 |
_ADCON0_DONE_POSITION | none | 0x1 |
_ADCON0_DONE_SIZE | none | 0x1 |
_ADCON0_DONE_LENGTH | none | 0x1 |
_ADCON0_DONE_MASK | none | 0x2 |
_ADCON0_CHS0_POSN | none | 0x2 |
_ADCON0_CHS0_POSITION | none | 0x2 |
_ADCON0_CHS0_SIZE | none | 0x1 |
_ADCON0_CHS0_LENGTH | none | 0x1 |
_ADCON0_CHS0_MASK | none | 0x4 |
_ADCON0_CHS1_POSN | none | 0x3 |
_ADCON0_CHS1_POSITION | none | 0x3 |
_ADCON0_CHS1_SIZE | none | 0x1 |
_ADCON0_CHS1_LENGTH | none | 0x1 |
_ADCON0_CHS1_MASK | none | 0x8 |
_ADCON0_CHS2_POSN | none | 0x4 |
_ADCON0_CHS2_POSITION | none | 0x4 |
_ADCON0_CHS2_SIZE | none | 0x1 |
_ADCON0_CHS2_LENGTH | none | 0x1 |
_ADCON0_CHS2_MASK | none | 0x10 |
_ADCON0_CHS3_POSN | none | 0x5 |
_ADCON0_CHS3_POSITION | none | 0x5 |
_ADCON0_CHS3_SIZE | none | 0x1 |
_ADCON0_CHS3_LENGTH | none | 0x1 |
_ADCON0_CHS3_MASK | none | 0x20 |
_ADCON0_GO_DONE_POSN | none | 0x1 |
_ADCON0_GO_DONE_POSITION | none | 0x1 |
_ADCON0_GO_DONE_SIZE | none | 0x1 |
_ADCON0_GO_DONE_LENGTH | none | 0x1 |
_ADCON0_GO_DONE_MASK | none | 0x2 |
_ADCON0_GO_POSN | none | 0x1 |
_ADCON0_GO_POSITION | none | 0x1 |
_ADCON0_GO_SIZE | none | 0x1 |
_ADCON0_GO_LENGTH | none | 0x1 |
_ADCON0_GO_MASK | none | 0x2 |
_ADCON0_NOT_DONE_POSN | none | 0x1 |
_ADCON0_NOT_DONE_POSITION | none | 0x1 |
_ADCON0_NOT_DONE_SIZE | none | 0x1 |
_ADCON0_NOT_DONE_LENGTH | none | 0x1 |
_ADCON0_NOT_DONE_MASK | none | 0x2 |
_ADCON0_nDONE_POSN | none | 0x1 |
_ADCON0_nDONE_POSITION | none | 0x1 |
_ADCON0_nDONE_SIZE | none | 0x1 |
_ADCON0_nDONE_LENGTH | none | 0x1 |
_ADCON0_nDONE_MASK | none | 0x2 |
_ADCON0_GODONE_POSN | none | 0x1 |
_ADCON0_GODONE_POSITION | none | 0x1 |
_ADCON0_GODONE_SIZE | none | 0x1 |
_ADCON0_GODONE_LENGTH | none | 0x1 |
_ADCON0_GODONE_MASK | none | 0x2 |
ADRES | none | <\077435>ADRES |
ADRES | none | <\077435>ADRES |
ADRESL | none | <\077435>ADRESL |
ADRESL | none | <\077435>ADRESL |
ADRESH | none | <\077435>ADRESH |
ADRESH | none | <\077435>ADRESH |
SSPCON2 | none | <\077435>SSPCON2 |
SSPCON2 | none | <\077435>SSPCON2 |
_SSPCON2_SEN_POSN | none | 0x0 |
_SSPCON2_SEN_POSITION | none | 0x0 |
_SSPCON2_SEN_SIZE | none | 0x1 |
_SSPCON2_SEN_LENGTH | none | 0x1 |
_SSPCON2_SEN_MASK | none | 0x1 |
_SSPCON2_RSEN_POSN | none | 0x1 |
_SSPCON2_RSEN_POSITION | none | 0x1 |
_SSPCON2_RSEN_SIZE | none | 0x1 |
_SSPCON2_RSEN_LENGTH | none | 0x1 |
_SSPCON2_RSEN_MASK | none | 0x2 |
_SSPCON2_PEN_POSN | none | 0x2 |
_SSPCON2_PEN_POSITION | none | 0x2 |
_SSPCON2_PEN_SIZE | none | 0x1 |
_SSPCON2_PEN_LENGTH | none | 0x1 |
_SSPCON2_PEN_MASK | none | 0x4 |
_SSPCON2_RCEN_POSN | none | 0x3 |
_SSPCON2_RCEN_POSITION | none | 0x3 |
_SSPCON2_RCEN_SIZE | none | 0x1 |
_SSPCON2_RCEN_LENGTH | none | 0x1 |
_SSPCON2_RCEN_MASK | none | 0x8 |
_SSPCON2_ACKEN_POSN | none | 0x4 |
_SSPCON2_ACKEN_POSITION | none | 0x4 |
_SSPCON2_ACKEN_SIZE | none | 0x1 |
_SSPCON2_ACKEN_LENGTH | none | 0x1 |
_SSPCON2_ACKEN_MASK | none | 0x10 |
_SSPCON2_ACKDT_POSN | none | 0x5 |
_SSPCON2_ACKDT_POSITION | none | 0x5 |
_SSPCON2_ACKDT_SIZE | none | 0x1 |
_SSPCON2_ACKDT_LENGTH | none | 0x1 |
_SSPCON2_ACKDT_MASK | none | 0x20 |
_SSPCON2_ACKSTAT_POSN | none | 0x6 |
_SSPCON2_ACKSTAT_POSITION | none | 0x6 |
_SSPCON2_ACKSTAT_SIZE | none | 0x1 |
_SSPCON2_ACKSTAT_LENGTH | none | 0x1 |
_SSPCON2_ACKSTAT_MASK | none | 0x40 |
_SSPCON2_GCEN_POSN | none | 0x7 |
_SSPCON2_GCEN_POSITION | none | 0x7 |
_SSPCON2_GCEN_SIZE | none | 0x1 |
_SSPCON2_GCEN_LENGTH | none | 0x1 |
_SSPCON2_GCEN_MASK | none | 0x80 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPCON1 | none | <\077435>SSPCON1 |
_SSPCON1_SSPM_POSN | none | 0x0 |
_SSPCON1_SSPM_POSITION | none | 0x0 |
_SSPCON1_SSPM_SIZE | none | 0x4 |
_SSPCON1_SSPM_LENGTH | none | 0x4 |
_SSPCON1_SSPM_MASK | none | 0xF |
_SSPCON1_CKP_POSN | none | 0x4 |
_SSPCON1_CKP_POSITION | none | 0x4 |
_SSPCON1_CKP_SIZE | none | 0x1 |
_SSPCON1_CKP_LENGTH | none | 0x1 |
_SSPCON1_CKP_MASK | none | 0x10 |
_SSPCON1_SSPEN_POSN | none | 0x5 |
_SSPCON1_SSPEN_POSITION | none | 0x5 |
_SSPCON1_SSPEN_SIZE | none | 0x1 |
_SSPCON1_SSPEN_LENGTH | none | 0x1 |
_SSPCON1_SSPEN_MASK | none | 0x20 |
_SSPCON1_SSPOV_POSN | none | 0x6 |
_SSPCON1_SSPOV_POSITION | none | 0x6 |
_SSPCON1_SSPOV_SIZE | none | 0x1 |
_SSPCON1_SSPOV_LENGTH | none | 0x1 |
_SSPCON1_SSPOV_MASK | none | 0x40 |
_SSPCON1_WCOL_POSN | none | 0x7 |
_SSPCON1_WCOL_POSITION | none | 0x7 |
_SSPCON1_WCOL_SIZE | none | 0x1 |
_SSPCON1_WCOL_LENGTH | none | 0x1 |
_SSPCON1_WCOL_MASK | none | 0x80 |
_SSPCON1_SSPM0_POSN | none | 0x0 |
_SSPCON1_SSPM0_POSITION | none | 0x0 |
_SSPCON1_SSPM0_SIZE | none | 0x1 |
_SSPCON1_SSPM0_LENGTH | none | 0x1 |
_SSPCON1_SSPM0_MASK | none | 0x1 |
_SSPCON1_SSPM1_POSN | none | 0x1 |
_SSPCON1_SSPM1_POSITION | none | 0x1 |
_SSPCON1_SSPM1_SIZE | none | 0x1 |
_SSPCON1_SSPM1_LENGTH | none | 0x1 |
_SSPCON1_SSPM1_MASK | none | 0x2 |
_SSPCON1_SSPM2_POSN | none | 0x2 |
_SSPCON1_SSPM2_POSITION | none | 0x2 |
_SSPCON1_SSPM2_SIZE | none | 0x1 |
_SSPCON1_SSPM2_LENGTH | none | 0x1 |
_SSPCON1_SSPM2_MASK | none | 0x4 |
_SSPCON1_SSPM3_POSN | none | 0x3 |
_SSPCON1_SSPM3_POSITION | none | 0x3 |
_SSPCON1_SSPM3_SIZE | none | 0x1 |
_SSPCON1_SSPM3_LENGTH | none | 0x1 |
_SSPCON1_SSPM3_MASK | none | 0x8 |
SSPSTAT | none | <\077435>SSPSTAT |
SSPSTAT | none | <\077435>SSPSTAT |
_SSPSTAT_R_NOT_W_POSN | none | 0x2 |
_SSPSTAT_R_NOT_W_POSITION | none | 0x2 |
_SSPSTAT_R_NOT_W_SIZE | none | 0x1 |
_SSPSTAT_R_NOT_W_LENGTH | none | 0x1 |
_SSPSTAT_R_NOT_W_MASK | none | 0x4 |
_SSPSTAT_D_NOT_A_POSN | none | 0x5 |
_SSPSTAT_D_NOT_A_POSITION | none | 0x5 |
_SSPSTAT_D_NOT_A_SIZE | none | 0x1 |
_SSPSTAT_D_NOT_A_LENGTH | none | 0x1 |
_SSPSTAT_D_NOT_A_MASK | none | 0x20 |
_SSPSTAT_BF_POSN | none | 0x0 |
_SSPSTAT_BF_POSITION | none | 0x0 |
_SSPSTAT_BF_SIZE | none | 0x1 |
_SSPSTAT_BF_LENGTH | none | 0x1 |
_SSPSTAT_BF_MASK | none | 0x1 |
_SSPSTAT_UA_POSN | none | 0x1 |
_SSPSTAT_UA_POSITION | none | 0x1 |
_SSPSTAT_UA_SIZE | none | 0x1 |
_SSPSTAT_UA_LENGTH | none | 0x1 |
_SSPSTAT_UA_MASK | none | 0x2 |
_SSPSTAT_R_nW_POSN | none | 0x2 |
_SSPSTAT_R_nW_POSITION | none | 0x2 |
_SSPSTAT_R_nW_SIZE | none | 0x1 |
_SSPSTAT_R_nW_LENGTH | none | 0x1 |
_SSPSTAT_R_nW_MASK | none | 0x4 |
_SSPSTAT_S_POSN | none | 0x3 |
_SSPSTAT_S_POSITION | none | 0x3 |
_SSPSTAT_S_SIZE | none | 0x1 |
_SSPSTAT_S_LENGTH | none | 0x1 |
_SSPSTAT_S_MASK | none | 0x8 |
_SSPSTAT_P_POSN | none | 0x4 |
_SSPSTAT_P_POSITION | none | 0x4 |
_SSPSTAT_P_SIZE | none | 0x1 |
_SSPSTAT_P_LENGTH | none | 0x1 |
_SSPSTAT_P_MASK | none | 0x10 |
_SSPSTAT_D_nA_POSN | none | 0x5 |
_SSPSTAT_D_nA_POSITION | none | 0x5 |
_SSPSTAT_D_nA_SIZE | none | 0x1 |
_SSPSTAT_D_nA_LENGTH | none | 0x1 |
_SSPSTAT_D_nA_MASK | none | 0x20 |
_SSPSTAT_CKE_POSN | none | 0x6 |
_SSPSTAT_CKE_POSITION | none | 0x6 |
_SSPSTAT_CKE_SIZE | none | 0x1 |
_SSPSTAT_CKE_LENGTH | none | 0x1 |
_SSPSTAT_CKE_MASK | none | 0x40 |
_SSPSTAT_SMP_POSN | none | 0x7 |
_SSPSTAT_SMP_POSITION | none | 0x7 |
_SSPSTAT_SMP_SIZE | none | 0x1 |
_SSPSTAT_SMP_LENGTH | none | 0x1 |
_SSPSTAT_SMP_MASK | none | 0x80 |
_SSPSTAT_R_W_POSN | none | 0x2 |
_SSPSTAT_R_W_POSITION | none | 0x2 |
_SSPSTAT_R_W_SIZE | none | 0x1 |
_SSPSTAT_R_W_LENGTH | none | 0x1 |
_SSPSTAT_R_W_MASK | none | 0x4 |
_SSPSTAT_D_A_POSN | none | 0x5 |
_SSPSTAT_D_A_POSITION | none | 0x5 |
_SSPSTAT_D_A_SIZE | none | 0x1 |
_SSPSTAT_D_A_LENGTH | none | 0x1 |
_SSPSTAT_D_A_MASK | none | 0x20 |
_SSPSTAT_I2C_READ_POSN | none | 0x2 |
_SSPSTAT_I2C_READ_POSITION | none | 0x2 |
_SSPSTAT_I2C_READ_SIZE | none | 0x1 |
_SSPSTAT_I2C_READ_LENGTH | none | 0x1 |
_SSPSTAT_I2C_READ_MASK | none | 0x4 |
_SSPSTAT_I2C_START_POSN | none | 0x3 |
_SSPSTAT_I2C_START_POSITION | none | 0x3 |
_SSPSTAT_I2C_START_SIZE | none | 0x1 |
_SSPSTAT_I2C_START_LENGTH | none | 0x1 |
_SSPSTAT_I2C_START_MASK | none | 0x8 |
_SSPSTAT_I2C_STOP_POSN | none | 0x4 |
_SSPSTAT_I2C_STOP_POSITION | none | 0x4 |
_SSPSTAT_I2C_STOP_SIZE | none | 0x1 |
_SSPSTAT_I2C_STOP_LENGTH | none | 0x1 |
_SSPSTAT_I2C_STOP_MASK | none | 0x10 |
_SSPSTAT_I2C_DAT_POSN | none | 0x5 |
_SSPSTAT_I2C_DAT_POSITION | none | 0x5 |
_SSPSTAT_I2C_DAT_SIZE | none | 0x1 |
_SSPSTAT_I2C_DAT_LENGTH | none | 0x1 |
_SSPSTAT_I2C_DAT_MASK | none | 0x20 |
_SSPSTAT_nW_POSN | none | 0x2 |
_SSPSTAT_nW_POSITION | none | 0x2 |
_SSPSTAT_nW_SIZE | none | 0x1 |
_SSPSTAT_nW_LENGTH | none | 0x1 |
_SSPSTAT_nW_MASK | none | 0x4 |
_SSPSTAT_nA_POSN | none | 0x5 |
_SSPSTAT_nA_POSITION | none | 0x5 |
_SSPSTAT_nA_SIZE | none | 0x1 |
_SSPSTAT_nA_LENGTH | none | 0x1 |
_SSPSTAT_nA_MASK | none | 0x20 |
_SSPSTAT_NOT_WRITE_POSN | none | 0x2 |
_SSPSTAT_NOT_WRITE_POSITION | none | 0x2 |
_SSPSTAT_NOT_WRITE_SIZE | none | 0x1 |
_SSPSTAT_NOT_WRITE_LENGTH | none | 0x1 |
_SSPSTAT_NOT_WRITE_MASK | none | 0x4 |
_SSPSTAT_NOT_ADDRESS_POSN | none | 0x5 |
_SSPSTAT_NOT_ADDRESS_POSITION | none | 0x5 |
_SSPSTAT_NOT_ADDRESS_SIZE | none | 0x1 |
_SSPSTAT_NOT_ADDRESS_LENGTH | none | 0x1 |
_SSPSTAT_NOT_ADDRESS_MASK | none | 0x20 |
_SSPSTAT_nWRITE_POSN | none | 0x2 |
_SSPSTAT_nWRITE_POSITION | none | 0x2 |
_SSPSTAT_nWRITE_SIZE | none | 0x1 |
_SSPSTAT_nWRITE_LENGTH | none | 0x1 |
_SSPSTAT_nWRITE_MASK | none | 0x4 |
_SSPSTAT_nADDRESS_POSN | none | 0x5 |
_SSPSTAT_nADDRESS_POSITION | none | 0x5 |
_SSPSTAT_nADDRESS_SIZE | none | 0x1 |
_SSPSTAT_nADDRESS_LENGTH | none | 0x1 |
_SSPSTAT_nADDRESS_MASK | none | 0x20 |
_SSPSTAT_READ_WRITE_POSN | none | 0x2 |
_SSPSTAT_READ_WRITE_POSITION | none | 0x2 |
_SSPSTAT_READ_WRITE_SIZE | none | 0x1 |
_SSPSTAT_READ_WRITE_LENGTH | none | 0x1 |
_SSPSTAT_READ_WRITE_MASK | none | 0x4 |
_SSPSTAT_DATA_ADDRESS_POSN | none | 0x5 |
_SSPSTAT_DATA_ADDRESS_POSITION | none | 0x5 |
_SSPSTAT_DATA_ADDRESS_SIZE | none | 0x1 |
_SSPSTAT_DATA_ADDRESS_LENGTH | none | 0x1 |
_SSPSTAT_DATA_ADDRESS_MASK | none | 0x20 |
_SSPSTAT_R_POSN | none | 0x2 |
_SSPSTAT_R_POSITION | none | 0x2 |
_SSPSTAT_R_SIZE | none | 0x1 |
_SSPSTAT_R_LENGTH | none | 0x1 |
_SSPSTAT_R_MASK | none | 0x4 |
_SSPSTAT_D_POSN | none | 0x5 |
_SSPSTAT_D_POSITION | none | 0x5 |
_SSPSTAT_D_SIZE | none | 0x1 |
_SSPSTAT_D_LENGTH | none | 0x1 |
_SSPSTAT_D_MASK | none | 0x20 |
_SSPSTAT_RW_POSN | none | 0x2 |
_SSPSTAT_RW_POSITION | none | 0x2 |
_SSPSTAT_RW_SIZE | none | 0x1 |
_SSPSTAT_RW_LENGTH | none | 0x1 |
_SSPSTAT_RW_MASK | none | 0x4 |
_SSPSTAT_START_POSN | none | 0x3 |
_SSPSTAT_START_POSITION | none | 0x3 |
_SSPSTAT_START_SIZE | none | 0x1 |
_SSPSTAT_START_LENGTH | none | 0x1 |
_SSPSTAT_START_MASK | none | 0x8 |
_SSPSTAT_STOP_POSN | none | 0x4 |
_SSPSTAT_STOP_POSITION | none | 0x4 |
_SSPSTAT_STOP_SIZE | none | 0x1 |
_SSPSTAT_STOP_LENGTH | none | 0x1 |
_SSPSTAT_STOP_MASK | none | 0x10 |
_SSPSTAT_DA_POSN | none | 0x5 |
_SSPSTAT_DA_POSITION | none | 0x5 |
_SSPSTAT_DA_SIZE | none | 0x1 |
_SSPSTAT_DA_LENGTH | none | 0x1 |
_SSPSTAT_DA_MASK | none | 0x20 |
_SSPSTAT_NOT_W_POSN | none | 0x2 |
_SSPSTAT_NOT_W_POSITION | none | 0x2 |
_SSPSTAT_NOT_W_SIZE | none | 0x1 |
_SSPSTAT_NOT_W_LENGTH | none | 0x1 |
_SSPSTAT_NOT_W_MASK | none | 0x4 |
_SSPSTAT_NOT_A_POSN | none | 0x5 |
_SSPSTAT_NOT_A_POSITION | none | 0x5 |
_SSPSTAT_NOT_A_SIZE | none | 0x1 |
_SSPSTAT_NOT_A_LENGTH | none | 0x1 |
_SSPSTAT_NOT_A_MASK | none | 0x20 |
SSPADD | none | <\077435>SSPADD |
SSPADD | none | <\077435>SSPADD |
SSPBUF | none | <\077435>SSPBUF |
SSPBUF | none | <\077435>SSPBUF |
T2CON | none | <\077435>T2CON |
T2CON | none | <\077435>T2CON |
_T2CON_T2CKPS_POSN | none | 0x0 |
_T2CON_T2CKPS_POSITION | none | 0x0 |
_T2CON_T2CKPS_SIZE | none | 0x2 |
_T2CON_T2CKPS_LENGTH | none | 0x2 |
_T2CON_T2CKPS_MASK | none | 0x3 |
_T2CON_TMR2ON_POSN | none | 0x2 |
_T2CON_TMR2ON_POSITION | none | 0x2 |
_T2CON_TMR2ON_SIZE | none | 0x1 |
_T2CON_TMR2ON_LENGTH | none | 0x1 |
_T2CON_TMR2ON_MASK | none | 0x4 |
_T2CON_T2OUTPS_POSN | none | 0x3 |
_T2CON_T2OUTPS_POSITION | none | 0x3 |
_T2CON_T2OUTPS_SIZE | none | 0x4 |
_T2CON_T2OUTPS_LENGTH | none | 0x4 |
_T2CON_T2OUTPS_MASK | none | 0x78 |
_T2CON_T2CKPS0_POSN | none | 0x0 |
_T2CON_T2CKPS0_POSITION | none | 0x0 |
_T2CON_T2CKPS0_SIZE | none | 0x1 |
_T2CON_T2CKPS0_LENGTH | none | 0x1 |
_T2CON_T2CKPS0_MASK | none | 0x1 |
_T2CON_T2CKPS1_POSN | none | 0x1 |
_T2CON_T2CKPS1_POSITION | none | 0x1 |
_T2CON_T2CKPS1_SIZE | none | 0x1 |
_T2CON_T2CKPS1_LENGTH | none | 0x1 |
_T2CON_T2CKPS1_MASK | none | 0x2 |
_T2CON_T2OUTPS0_POSN | none | 0x3 |
_T2CON_T2OUTPS0_POSITION | none | 0x3 |
_T2CON_T2OUTPS0_SIZE | none | 0x1 |
_T2CON_T2OUTPS0_LENGTH | none | 0x1 |
_T2CON_T2OUTPS0_MASK | none | 0x8 |
_T2CON_T2OUTPS1_POSN | none | 0x4 |
_T2CON_T2OUTPS1_POSITION | none | 0x4 |
_T2CON_T2OUTPS1_SIZE | none | 0x1 |
_T2CON_T2OUTPS1_LENGTH | none | 0x1 |
_T2CON_T2OUTPS1_MASK | none | 0x10 |
_T2CON_T2OUTPS2_POSN | none | 0x5 |
_T2CON_T2OUTPS2_POSITION | none | 0x5 |
_T2CON_T2OUTPS2_SIZE | none | 0x1 |
_T2CON_T2OUTPS2_LENGTH | none | 0x1 |
_T2CON_T2OUTPS2_MASK | none | 0x20 |
_T2CON_T2OUTPS3_POSN | none | 0x6 |
_T2CON_T2OUTPS3_POSITION | none | 0x6 |
_T2CON_T2OUTPS3_SIZE | none | 0x1 |
_T2CON_T2OUTPS3_LENGTH | none | 0x1 |
_T2CON_T2OUTPS3_MASK | none | 0x40 |
PR2 | none | <\077435>PR2 |
PR2 | none | <\077435>PR2 |
TMR2 | none | <\077435>TMR2 |
TMR2 | none | <\077435>TMR2 |
T1CON | none | <\077435>T1CON |
T1CON | none | <\077435>T1CON |
_T1CON_NOT_T1SYNC_POSN | none | 0x2 |
_T1CON_NOT_T1SYNC_POSITION | none | 0x2 |
_T1CON_NOT_T1SYNC_SIZE | none | 0x1 |
_T1CON_NOT_T1SYNC_LENGTH | none | 0x1 |
_T1CON_NOT_T1SYNC_MASK | none | 0x4 |
_T1CON_TMR1ON_POSN | none | 0x0 |
_T1CON_TMR1ON_POSITION | none | 0x0 |
_T1CON_TMR1ON_SIZE | none | 0x1 |
_T1CON_TMR1ON_LENGTH | none | 0x1 |
_T1CON_TMR1ON_MASK | none | 0x1 |
_T1CON_TMR1CS_POSN | none | 0x1 |
_T1CON_TMR1CS_POSITION | none | 0x1 |
_T1CON_TMR1CS_SIZE | none | 0x1 |
_T1CON_TMR1CS_LENGTH | none | 0x1 |
_T1CON_TMR1CS_MASK | none | 0x2 |
_T1CON_nT1SYNC_POSN | none | 0x2 |
_T1CON_nT1SYNC_POSITION | none | 0x2 |
_T1CON_nT1SYNC_SIZE | none | 0x1 |
_T1CON_nT1SYNC_LENGTH | none | 0x1 |
_T1CON_nT1SYNC_MASK | none | 0x4 |
_T1CON_T1OSCEN_POSN | none | 0x3 |
_T1CON_T1OSCEN_POSITION | none | 0x3 |
_T1CON_T1OSCEN_SIZE | none | 0x1 |
_T1CON_T1OSCEN_LENGTH | none | 0x1 |
_T1CON_T1OSCEN_MASK | none | 0x8 |
_T1CON_T1CKPS_POSN | none | 0x4 |
_T1CON_T1CKPS_POSITION | none | 0x4 |
_T1CON_T1CKPS_SIZE | none | 0x2 |
_T1CON_T1CKPS_LENGTH | none | 0x2 |
_T1CON_T1CKPS_MASK | none | 0x30 |
_T1CON_RD16_POSN | none | 0x7 |
_T1CON_RD16_POSITION | none | 0x7 |
_T1CON_RD16_SIZE | none | 0x1 |
_T1CON_RD16_LENGTH | none | 0x1 |
_T1CON_RD16_MASK | none | 0x80 |
_T1CON_T1SYNC_POSN | none | 0x2 |
_T1CON_T1SYNC_POSITION | none | 0x2 |
_T1CON_T1SYNC_SIZE | none | 0x1 |
_T1CON_T1SYNC_LENGTH | none | 0x1 |
_T1CON_T1SYNC_MASK | none | 0x4 |
_T1CON_T1CKPS0_POSN | none | 0x4 |
_T1CON_T1CKPS0_POSITION | none | 0x4 |
_T1CON_T1CKPS0_SIZE | none | 0x1 |
_T1CON_T1CKPS0_LENGTH | none | 0x1 |
_T1CON_T1CKPS0_MASK | none | 0x10 |
_T1CON_T1CKPS1_POSN | none | 0x5 |
_T1CON_T1CKPS1_POSITION | none | 0x5 |
_T1CON_T1CKPS1_SIZE | none | 0x1 |
_T1CON_T1CKPS1_LENGTH | none | 0x1 |
_T1CON_T1CKPS1_MASK | none | 0x20 |
_T1CON_T1INSYNC_POSN | none | 0x2 |
_T1CON_T1INSYNC_POSITION | none | 0x2 |
_T1CON_T1INSYNC_SIZE | none | 0x1 |
_T1CON_T1INSYNC_LENGTH | none | 0x1 |
_T1CON_T1INSYNC_MASK | none | 0x4 |
_T1CON_SOSCEN_POSN | none | 0x3 |
_T1CON_SOSCEN_POSITION | none | 0x3 |
_T1CON_SOSCEN_SIZE | none | 0x1 |
_T1CON_SOSCEN_LENGTH | none | 0x1 |
_T1CON_SOSCEN_MASK | none | 0x8 |
_T1CON_T1RD16_POSN | none | 0x7 |
_T1CON_T1RD16_POSITION | none | 0x7 |
_T1CON_T1RD16_SIZE | none | 0x1 |
_T1CON_T1RD16_LENGTH | none | 0x1 |
_T1CON_T1RD16_MASK | none | 0x80 |
TMR1 | none | <\077435>TMR1 |
TMR1 | none | <\077435>TMR1 |
TMR1L | none | <\077435>TMR1L |
TMR1L | none | <\077435>TMR1L |
TMR1H | none | <\077435>TMR1H |
TMR1H | none | <\077435>TMR1H |
RCON | none | <\077435>RCON |
RCON | none | <\077435>RCON |
_RCON_NOT_BOR_POSN | none | 0x0 |
_RCON_NOT_BOR_POSITION | none | 0x0 |
_RCON_NOT_BOR_SIZE | none | 0x1 |
_RCON_NOT_BOR_LENGTH | none | 0x1 |
_RCON_NOT_BOR_MASK | none | 0x1 |
_RCON_NOT_POR_POSN | none | 0x1 |
_RCON_NOT_POR_POSITION | none | 0x1 |
_RCON_NOT_POR_SIZE | none | 0x1 |
_RCON_NOT_POR_LENGTH | none | 0x1 |
_RCON_NOT_POR_MASK | none | 0x2 |
_RCON_NOT_PD_POSN | none | 0x2 |
_RCON_NOT_PD_POSITION | none | 0x2 |
_RCON_NOT_PD_SIZE | none | 0x1 |
_RCON_NOT_PD_LENGTH | none | 0x1 |
_RCON_NOT_PD_MASK | none | 0x4 |
_RCON_NOT_TO_POSN | none | 0x3 |
_RCON_NOT_TO_POSITION | none | 0x3 |
_RCON_NOT_TO_SIZE | none | 0x1 |
_RCON_NOT_TO_LENGTH | none | 0x1 |
_RCON_NOT_TO_MASK | none | 0x8 |
_RCON_NOT_RI_POSN | none | 0x4 |
_RCON_NOT_RI_POSITION | none | 0x4 |
_RCON_NOT_RI_SIZE | none | 0x1 |
_RCON_NOT_RI_LENGTH | none | 0x1 |
_RCON_NOT_RI_MASK | none | 0x10 |
_RCON_nBOR_POSN | none | 0x0 |
_RCON_nBOR_POSITION | none | 0x0 |
_RCON_nBOR_SIZE | none | 0x1 |
_RCON_nBOR_LENGTH | none | 0x1 |
_RCON_nBOR_MASK | none | 0x1 |
_RCON_nPOR_POSN | none | 0x1 |
_RCON_nPOR_POSITION | none | 0x1 |
_RCON_nPOR_SIZE | none | 0x1 |
_RCON_nPOR_LENGTH | none | 0x1 |
_RCON_nPOR_MASK | none | 0x2 |
_RCON_nPD_POSN | none | 0x2 |
_RCON_nPD_POSITION | none | 0x2 |
_RCON_nPD_SIZE | none | 0x1 |
_RCON_nPD_LENGTH | none | 0x1 |
_RCON_nPD_MASK | none | 0x4 |
_RCON_nTO_POSN | none | 0x3 |
_RCON_nTO_POSITION | none | 0x3 |
_RCON_nTO_SIZE | none | 0x1 |
_RCON_nTO_LENGTH | none | 0x1 |
_RCON_nTO_MASK | none | 0x8 |
_RCON_nRI_POSN | none | 0x4 |
_RCON_nRI_POSITION | none | 0x4 |
_RCON_nRI_SIZE | none | 0x1 |
_RCON_nRI_LENGTH | none | 0x1 |
_RCON_nRI_MASK | none | 0x10 |
_RCON_IPEN_POSN | none | 0x7 |
_RCON_IPEN_POSITION | none | 0x7 |
_RCON_IPEN_SIZE | none | 0x1 |
_RCON_IPEN_LENGTH | none | 0x1 |
_RCON_IPEN_MASK | none | 0x80 |
_RCON_NOT_IPEN_POSN | none | 0x7 |
_RCON_NOT_IPEN_POSITION | none | 0x7 |
_RCON_NOT_IPEN_SIZE | none | 0x1 |
_RCON_NOT_IPEN_LENGTH | none | 0x1 |
_RCON_NOT_IPEN_MASK | none | 0x80 |
_RCON_BOR_POSN | none | 0x0 |
_RCON_BOR_POSITION | none | 0x0 |
_RCON_BOR_SIZE | none | 0x1 |
_RCON_BOR_LENGTH | none | 0x1 |
_RCON_BOR_MASK | none | 0x1 |
_RCON_POR_POSN | none | 0x1 |
_RCON_POR_POSITION | none | 0x1 |
_RCON_POR_SIZE | none | 0x1 |
_RCON_POR_LENGTH | none | 0x1 |
_RCON_POR_MASK | none | 0x2 |
_RCON_PD_POSN | none | 0x2 |
_RCON_PD_POSITION | none | 0x2 |
_RCON_PD_SIZE | none | 0x1 |
_RCON_PD_LENGTH | none | 0x1 |
_RCON_PD_MASK | none | 0x4 |
_RCON_TO_POSN | none | 0x3 |
_RCON_TO_POSITION | none | 0x3 |
_RCON_TO_SIZE | none | 0x1 |
_RCON_TO_LENGTH | none | 0x1 |
_RCON_TO_MASK | none | 0x8 |
_RCON_RI_POSN | none | 0x4 |
_RCON_RI_POSITION | none | 0x4 |
_RCON_RI_SIZE | none | 0x1 |
_RCON_RI_LENGTH | none | 0x1 |
_RCON_RI_MASK | none | 0x10 |
_RCON_nIPEN_POSN | none | 0x7 |
_RCON_nIPEN_POSITION | none | 0x7 |
_RCON_nIPEN_SIZE | none | 0x1 |
_RCON_nIPEN_LENGTH | none | 0x1 |
_RCON_nIPEN_MASK | none | 0x80 |
WDTCON | none | <\077435>WDTCON |
WDTCON | none | <\077435>WDTCON |
_WDTCON_SWDTEN_POSN | none | 0x0 |
_WDTCON_SWDTEN_POSITION | none | 0x0 |
_WDTCON_SWDTEN_SIZE | none | 0x1 |
_WDTCON_SWDTEN_LENGTH | none | 0x1 |
_WDTCON_SWDTEN_MASK | none | 0x1 |
_WDTCON_SWDTE_POSN | none | 0x0 |
_WDTCON_SWDTE_POSITION | none | 0x0 |
_WDTCON_SWDTE_SIZE | none | 0x1 |
_WDTCON_SWDTE_LENGTH | none | 0x1 |
_WDTCON_SWDTE_MASK | none | 0x1 |
LVDCON | none | <\077435>LVDCON |
LVDCON | none | <\077435>LVDCON |
_LVDCON_LVDL_POSN | none | 0x0 |
_LVDCON_LVDL_POSITION | none | 0x0 |
_LVDCON_LVDL_SIZE | none | 0x4 |
_LVDCON_LVDL_LENGTH | none | 0x4 |
_LVDCON_LVDL_MASK | none | 0xF |
_LVDCON_LVDEN_POSN | none | 0x4 |
_LVDCON_LVDEN_POSITION | none | 0x4 |
_LVDCON_LVDEN_SIZE | none | 0x1 |
_LVDCON_LVDEN_LENGTH | none | 0x1 |
_LVDCON_LVDEN_MASK | none | 0x10 |
_LVDCON_IRVST_POSN | none | 0x5 |
_LVDCON_IRVST_POSITION | none | 0x5 |
_LVDCON_IRVST_SIZE | none | 0x1 |
_LVDCON_IRVST_LENGTH | none | 0x1 |
_LVDCON_IRVST_MASK | none | 0x20 |
_LVDCON_LVDL0_POSN | none | 0x0 |
_LVDCON_LVDL0_POSITION | none | 0x0 |
_LVDCON_LVDL0_SIZE | none | 0x1 |
_LVDCON_LVDL0_LENGTH | none | 0x1 |
_LVDCON_LVDL0_MASK | none | 0x1 |
_LVDCON_LVDL1_POSN | none | 0x1 |
_LVDCON_LVDL1_POSITION | none | 0x1 |
_LVDCON_LVDL1_SIZE | none | 0x1 |
_LVDCON_LVDL1_LENGTH | none | 0x1 |
_LVDCON_LVDL1_MASK | none | 0x2 |
_LVDCON_LVDL2_POSN | none | 0x2 |
_LVDCON_LVDL2_POSITION | none | 0x2 |
_LVDCON_LVDL2_SIZE | none | 0x1 |
_LVDCON_LVDL2_LENGTH | none | 0x1 |
_LVDCON_LVDL2_MASK | none | 0x4 |
_LVDCON_LVDL3_POSN | none | 0x3 |
_LVDCON_LVDL3_POSITION | none | 0x3 |
_LVDCON_LVDL3_SIZE | none | 0x1 |
_LVDCON_LVDL3_LENGTH | none | 0x1 |
_LVDCON_LVDL3_MASK | none | 0x8 |
_LVDCON_LVV0_POSN | none | 0x0 |
_LVDCON_LVV0_POSITION | none | 0x0 |
_LVDCON_LVV0_SIZE | none | 0x1 |
_LVDCON_LVV0_LENGTH | none | 0x1 |
_LVDCON_LVV0_MASK | none | 0x1 |
_LVDCON_LVV1_POSN | none | 0x1 |
_LVDCON_LVV1_POSITION | none | 0x1 |
_LVDCON_LVV1_SIZE | none | 0x1 |
_LVDCON_LVV1_LENGTH | none | 0x1 |
_LVDCON_LVV1_MASK | none | 0x2 |
_LVDCON_LVV2_POSN | none | 0x2 |
_LVDCON_LVV2_POSITION | none | 0x2 |
_LVDCON_LVV2_SIZE | none | 0x1 |
_LVDCON_LVV2_LENGTH | none | 0x1 |
_LVDCON_LVV2_MASK | none | 0x4 |
_LVDCON_LVV3_POSN | none | 0x3 |
_LVDCON_LVV3_POSITION | none | 0x3 |
_LVDCON_LVV3_SIZE | none | 0x1 |
_LVDCON_LVV3_LENGTH | none | 0x1 |
_LVDCON_LVV3_MASK | none | 0x8 |
_LVDCON_BGST_POSN | none | 0x5 |
_LVDCON_BGST_POSITION | none | 0x5 |
_LVDCON_BGST_SIZE | none | 0x1 |
_LVDCON_BGST_LENGTH | none | 0x1 |
_LVDCON_BGST_MASK | none | 0x20 |
OSCCON | none | <\077435>OSCCON |
OSCCON | none | <\077435>OSCCON |
_OSCCON_SCS_POSN | none | 0x0 |
_OSCCON_SCS_POSITION | none | 0x0 |
_OSCCON_SCS_SIZE | none | 0x1 |
_OSCCON_SCS_LENGTH | none | 0x1 |
_OSCCON_SCS_MASK | none | 0x1 |
T0CON | none | <\077435>T0CON |
T0CON | none | <\077435>T0CON |
_T0CON_T0PS_POSN | none | 0x0 |
_T0CON_T0PS_POSITION | none | 0x0 |
_T0CON_T0PS_SIZE | none | 0x3 |
_T0CON_T0PS_LENGTH | none | 0x3 |
_T0CON_T0PS_MASK | none | 0x7 |
_T0CON_PSA_POSN | none | 0x3 |
_T0CON_PSA_POSITION | none | 0x3 |
_T0CON_PSA_SIZE | none | 0x1 |
_T0CON_PSA_LENGTH | none | 0x1 |
_T0CON_PSA_MASK | none | 0x8 |
_T0CON_T0SE_POSN | none | 0x4 |
_T0CON_T0SE_POSITION | none | 0x4 |
_T0CON_T0SE_SIZE | none | 0x1 |
_T0CON_T0SE_LENGTH | none | 0x1 |
_T0CON_T0SE_MASK | none | 0x10 |
_T0CON_T0CS_POSN | none | 0x5 |
_T0CON_T0CS_POSITION | none | 0x5 |
_T0CON_T0CS_SIZE | none | 0x1 |
_T0CON_T0CS_LENGTH | none | 0x1 |
_T0CON_T0CS_MASK | none | 0x20 |
_T0CON_T08BIT_POSN | none | 0x6 |
_T0CON_T08BIT_POSITION | none | 0x6 |
_T0CON_T08BIT_SIZE | none | 0x1 |
_T0CON_T08BIT_LENGTH | none | 0x1 |
_T0CON_T08BIT_MASK | none | 0x40 |
_T0CON_TMR0ON_POSN | none | 0x7 |
_T0CON_TMR0ON_POSITION | none | 0x7 |
_T0CON_TMR0ON_SIZE | none | 0x1 |
_T0CON_TMR0ON_LENGTH | none | 0x1 |
_T0CON_TMR0ON_MASK | none | 0x80 |
_T0CON_T0PS0_POSN | none | 0x0 |
_T0CON_T0PS0_POSITION | none | 0x0 |
_T0CON_T0PS0_SIZE | none | 0x1 |
_T0CON_T0PS0_LENGTH | none | 0x1 |
_T0CON_T0PS0_MASK | none | 0x1 |
_T0CON_T0PS1_POSN | none | 0x1 |
_T0CON_T0PS1_POSITION | none | 0x1 |
_T0CON_T0PS1_SIZE | none | 0x1 |
_T0CON_T0PS1_LENGTH | none | 0x1 |
_T0CON_T0PS1_MASK | none | 0x2 |
_T0CON_T0PS2_POSN | none | 0x2 |
_T0CON_T0PS2_POSITION | none | 0x2 |
_T0CON_T0PS2_SIZE | none | 0x1 |
_T0CON_T0PS2_LENGTH | none | 0x1 |
_T0CON_T0PS2_MASK | none | 0x4 |
TMR0 | none | <\077435>TMR0 |
TMR0 | none | <\077435>TMR0 |
TMR0L | none | <\077435>TMR0L |
TMR0L | none | <\077435>TMR0L |
TMR0H | none | <\077435>TMR0H |
TMR0H | none | <\077435>TMR0H |
STATUS | none | <\077435>STATUS |
STATUS | none | <\077435>STATUS |
_STATUS_C_POSN | none | 0x0 |
_STATUS_C_POSITION | none | 0x0 |
_STATUS_C_SIZE | none | 0x1 |
_STATUS_C_LENGTH | none | 0x1 |
_STATUS_C_MASK | none | 0x1 |
_STATUS_DC_POSN | none | 0x1 |
_STATUS_DC_POSITION | none | 0x1 |
_STATUS_DC_SIZE | none | 0x1 |
_STATUS_DC_LENGTH | none | 0x1 |
_STATUS_DC_MASK | none | 0x2 |
_STATUS_Z_POSN | none | 0x2 |
_STATUS_Z_POSITION | none | 0x2 |
_STATUS_Z_SIZE | none | 0x1 |
_STATUS_Z_LENGTH | none | 0x1 |
_STATUS_Z_MASK | none | 0x4 |
_STATUS_OV_POSN | none | 0x3 |
_STATUS_OV_POSITION | none | 0x3 |
_STATUS_OV_SIZE | none | 0x1 |
_STATUS_OV_LENGTH | none | 0x1 |
_STATUS_OV_MASK | none | 0x8 |
_STATUS_N_POSN | none | 0x4 |
_STATUS_N_POSITION | none | 0x4 |
_STATUS_N_SIZE | none | 0x1 |
_STATUS_N_LENGTH | none | 0x1 |
_STATUS_N_MASK | none | 0x10 |
_STATUS_CARRY_POSN | none | 0x0 |
_STATUS_CARRY_POSITION | none | 0x0 |
_STATUS_CARRY_SIZE | none | 0x1 |
_STATUS_CARRY_LENGTH | none | 0x1 |
_STATUS_CARRY_MASK | none | 0x1 |
_STATUS_ZERO_POSN | none | 0x2 |
_STATUS_ZERO_POSITION | none | 0x2 |
_STATUS_ZERO_SIZE | none | 0x1 |
_STATUS_ZERO_LENGTH | none | 0x1 |
_STATUS_ZERO_MASK | none | 0x4 |
_STATUS_OVERFLOW_POSN | none | 0x3 |
_STATUS_OVERFLOW_POSITION | none | 0x3 |
_STATUS_OVERFLOW_SIZE | none | 0x1 |
_STATUS_OVERFLOW_LENGTH | none | 0x1 |
_STATUS_OVERFLOW_MASK | none | 0x8 |
_STATUS_NEGATIVE_POSN | none | 0x4 |
_STATUS_NEGATIVE_POSITION | none | 0x4 |
_STATUS_NEGATIVE_SIZE | none | 0x1 |
_STATUS_NEGATIVE_LENGTH | none | 0x1 |
_STATUS_NEGATIVE_MASK | none | 0x10 |
FSR2 | none | <\077435>FSR2 |
FSR2 | none | <\077435>FSR2 |
FSR2L | none | <\077435>FSR2L |
FSR2L | none | <\077435>FSR2L |
FSR2H | none | <\077435>FSR2H |
FSR2H | none | <\077435>FSR2H |
PLUSW2 | none | <\077435>PLUSW2 |
PLUSW2 | none | <\077435>PLUSW2 |
PREINC2 | none | <\077435>PREINC2 |
PREINC2 | none | <\077435>PREINC2 |
POSTDEC2 | none | <\077435>POSTDEC2 |
POSTDEC2 | none | <\077435>POSTDEC2 |
POSTINC2 | none | <\077435>POSTINC2 |
POSTINC2 | none | <\077435>POSTINC2 |
INDF2 | none | <\077435>INDF2 |
INDF2 | none | <\077435>INDF2 |
BSR | none | <\077435>BSR |
BSR | none | <\077435>BSR |
FSR1 | none | <\077435>FSR1 |
FSR1 | none | <\077435>FSR1 |
FSR1L | none | <\077435>FSR1L |
FSR1L | none | <\077435>FSR1L |
FSR1H | none | <\077435>FSR1H |
FSR1H | none | <\077435>FSR1H |
PLUSW1 | none | <\077435>PLUSW1 |
PLUSW1 | none | <\077435>PLUSW1 |
PREINC1 | none | <\077435>PREINC1 |
PREINC1 | none | <\077435>PREINC1 |
POSTDEC1 | none | <\077435>POSTDEC1 |
POSTDEC1 | none | <\077435>POSTDEC1 |
POSTINC1 | none | <\077435>POSTINC1 |
POSTINC1 | none | <\077435>POSTINC1 |
INDF1 | none | <\077435>INDF1 |
INDF1 | none | <\077435>INDF1 |
WREG | none | <\077435>WREG |
WREG | none | <\077435>WREG |
FSR0 | none | <\077435>FSR0 |
FSR0 | none | <\077435>FSR0 |
FSR0L | none | <\077435>FSR0L |
FSR0L | none | <\077435>FSR0L |
FSR0H | none | <\077435>FSR0H |
FSR0H | none | <\077435>FSR0H |
PLUSW0 | none | <\077435>PLUSW0 |
PLUSW0 | none | <\077435>PLUSW0 |
PREINC0 | none | <\077435>PREINC0 |
PREINC0 | none | <\077435>PREINC0 |
POSTDEC0 | none | <\077435>POSTDEC0 |
POSTDEC0 | none | <\077435>POSTDEC0 |
POSTINC0 | none | <\077435>POSTINC0 |
POSTINC0 | none | <\077435>POSTINC0 |
INDF0 | none | <\077435>INDF0 |
INDF0 | none | <\077435>INDF0 |
INTCON3 | none | <\077435>INTCON3 |
INTCON3 | none | <\077435>INTCON3 |
_INTCON3_INT1IF_POSN | none | 0x0 |
_INTCON3_INT1IF_POSITION | none | 0x0 |
_INTCON3_INT1IF_SIZE | none | 0x1 |
_INTCON3_INT1IF_LENGTH | none | 0x1 |
_INTCON3_INT1IF_MASK | none | 0x1 |
_INTCON3_INT2IF_POSN | none | 0x1 |
_INTCON3_INT2IF_POSITION | none | 0x1 |
_INTCON3_INT2IF_SIZE | none | 0x1 |
_INTCON3_INT2IF_LENGTH | none | 0x1 |
_INTCON3_INT2IF_MASK | none | 0x2 |
_INTCON3_INT3IF_POSN | none | 0x2 |
_INTCON3_INT3IF_POSITION | none | 0x2 |
_INTCON3_INT3IF_SIZE | none | 0x1 |
_INTCON3_INT3IF_LENGTH | none | 0x1 |
_INTCON3_INT3IF_MASK | none | 0x4 |
_INTCON3_INT1IE_POSN | none | 0x3 |
_INTCON3_INT1IE_POSITION | none | 0x3 |
_INTCON3_INT1IE_SIZE | none | 0x1 |
_INTCON3_INT1IE_LENGTH | none | 0x1 |
_INTCON3_INT1IE_MASK | none | 0x8 |
_INTCON3_INT2IE_POSN | none | 0x4 |
_INTCON3_INT2IE_POSITION | none | 0x4 |
_INTCON3_INT2IE_SIZE | none | 0x1 |
_INTCON3_INT2IE_LENGTH | none | 0x1 |
_INTCON3_INT2IE_MASK | none | 0x10 |
_INTCON3_INT3IE_POSN | none | 0x5 |
_INTCON3_INT3IE_POSITION | none | 0x5 |
_INTCON3_INT3IE_SIZE | none | 0x1 |
_INTCON3_INT3IE_LENGTH | none | 0x1 |
_INTCON3_INT3IE_MASK | none | 0x20 |
_INTCON3_INT1IP_POSN | none | 0x6 |
_INTCON3_INT1IP_POSITION | none | 0x6 |
_INTCON3_INT1IP_SIZE | none | 0x1 |
_INTCON3_INT1IP_LENGTH | none | 0x1 |
_INTCON3_INT1IP_MASK | none | 0x40 |
_INTCON3_INT2IP_POSN | none | 0x7 |
_INTCON3_INT2IP_POSITION | none | 0x7 |
_INTCON3_INT2IP_SIZE | none | 0x1 |
_INTCON3_INT2IP_LENGTH | none | 0x1 |
_INTCON3_INT2IP_MASK | none | 0x80 |
_INTCON3_INT1F_POSN | none | 0x0 |
_INTCON3_INT1F_POSITION | none | 0x0 |
_INTCON3_INT1F_SIZE | none | 0x1 |
_INTCON3_INT1F_LENGTH | none | 0x1 |
_INTCON3_INT1F_MASK | none | 0x1 |
_INTCON3_INT2F_POSN | none | 0x1 |
_INTCON3_INT2F_POSITION | none | 0x1 |
_INTCON3_INT2F_SIZE | none | 0x1 |
_INTCON3_INT2F_LENGTH | none | 0x1 |
_INTCON3_INT2F_MASK | none | 0x2 |
_INTCON3_INT3F_POSN | none | 0x2 |
_INTCON3_INT3F_POSITION | none | 0x2 |
_INTCON3_INT3F_SIZE | none | 0x1 |
_INTCON3_INT3F_LENGTH | none | 0x1 |
_INTCON3_INT3F_MASK | none | 0x4 |
_INTCON3_INT1E_POSN | none | 0x3 |
_INTCON3_INT1E_POSITION | none | 0x3 |
_INTCON3_INT1E_SIZE | none | 0x1 |
_INTCON3_INT1E_LENGTH | none | 0x1 |
_INTCON3_INT1E_MASK | none | 0x8 |
_INTCON3_INT2E_POSN | none | 0x4 |
_INTCON3_INT2E_POSITION | none | 0x4 |
_INTCON3_INT2E_SIZE | none | 0x1 |
_INTCON3_INT2E_LENGTH | none | 0x1 |
_INTCON3_INT2E_MASK | none | 0x10 |
_INTCON3_INT3E_POSN | none | 0x5 |
_INTCON3_INT3E_POSITION | none | 0x5 |
_INTCON3_INT3E_SIZE | none | 0x1 |
_INTCON3_INT3E_LENGTH | none | 0x1 |
_INTCON3_INT3E_MASK | none | 0x20 |
_INTCON3_INT1P_POSN | none | 0x6 |
_INTCON3_INT1P_POSITION | none | 0x6 |
_INTCON3_INT1P_SIZE | none | 0x1 |
_INTCON3_INT1P_LENGTH | none | 0x1 |
_INTCON3_INT1P_MASK | none | 0x40 |
_INTCON3_INT2P_POSN | none | 0x7 |
_INTCON3_INT2P_POSITION | none | 0x7 |
_INTCON3_INT2P_SIZE | none | 0x1 |
_INTCON3_INT2P_LENGTH | none | 0x1 |
_INTCON3_INT2P_MASK | none | 0x80 |
INTCON2 | none | <\077435>INTCON2 |
INTCON2 | none | <\077435>INTCON2 |
_INTCON2_NOT_RBPU_POSN | none | 0x7 |
_INTCON2_NOT_RBPU_POSITION | none | 0x7 |
_INTCON2_NOT_RBPU_SIZE | none | 0x1 |
_INTCON2_NOT_RBPU_LENGTH | none | 0x1 |
_INTCON2_NOT_RBPU_MASK | none | 0x80 |
_INTCON2_RBIP_POSN | none | 0x0 |
_INTCON2_RBIP_POSITION | none | 0x0 |
_INTCON2_RBIP_SIZE | none | 0x1 |
_INTCON2_RBIP_LENGTH | none | 0x1 |
_INTCON2_RBIP_MASK | none | 0x1 |
_INTCON2_INT3IP_POSN | none | 0x1 |
_INTCON2_INT3IP_POSITION | none | 0x1 |
_INTCON2_INT3IP_SIZE | none | 0x1 |
_INTCON2_INT3IP_LENGTH | none | 0x1 |
_INTCON2_INT3IP_MASK | none | 0x2 |
_INTCON2_TMR0IP_POSN | none | 0x2 |
_INTCON2_TMR0IP_POSITION | none | 0x2 |
_INTCON2_TMR0IP_SIZE | none | 0x1 |
_INTCON2_TMR0IP_LENGTH | none | 0x1 |
_INTCON2_TMR0IP_MASK | none | 0x4 |
_INTCON2_INTEDG3_POSN | none | 0x3 |
_INTCON2_INTEDG3_POSITION | none | 0x3 |
_INTCON2_INTEDG3_SIZE | none | 0x1 |
_INTCON2_INTEDG3_LENGTH | none | 0x1 |
_INTCON2_INTEDG3_MASK | none | 0x8 |
_INTCON2_INTEDG2_POSN | none | 0x4 |
_INTCON2_INTEDG2_POSITION | none | 0x4 |
_INTCON2_INTEDG2_SIZE | none | 0x1 |
_INTCON2_INTEDG2_LENGTH | none | 0x1 |
_INTCON2_INTEDG2_MASK | none | 0x10 |
_INTCON2_INTEDG1_POSN | none | 0x5 |
_INTCON2_INTEDG1_POSITION | none | 0x5 |
_INTCON2_INTEDG1_SIZE | none | 0x1 |
_INTCON2_INTEDG1_LENGTH | none | 0x1 |
_INTCON2_INTEDG1_MASK | none | 0x20 |
_INTCON2_INTEDG0_POSN | none | 0x6 |
_INTCON2_INTEDG0_POSITION | none | 0x6 |
_INTCON2_INTEDG0_SIZE | none | 0x1 |
_INTCON2_INTEDG0_LENGTH | none | 0x1 |
_INTCON2_INTEDG0_MASK | none | 0x40 |
_INTCON2_nRBPU_POSN | none | 0x7 |
_INTCON2_nRBPU_POSITION | none | 0x7 |
_INTCON2_nRBPU_SIZE | none | 0x1 |
_INTCON2_nRBPU_LENGTH | none | 0x1 |
_INTCON2_nRBPU_MASK | none | 0x80 |
_INTCON2_INT3P_POSN | none | 0x1 |
_INTCON2_INT3P_POSITION | none | 0x1 |
_INTCON2_INT3P_SIZE | none | 0x1 |
_INTCON2_INT3P_LENGTH | none | 0x1 |
_INTCON2_INT3P_MASK | none | 0x2 |
_INTCON2_T0IP_POSN | none | 0x2 |
_INTCON2_T0IP_POSITION | none | 0x2 |
_INTCON2_T0IP_SIZE | none | 0x1 |
_INTCON2_T0IP_LENGTH | none | 0x1 |
_INTCON2_T0IP_MASK | none | 0x4 |
_INTCON2_RBPU_POSN | none | 0x7 |
_INTCON2_RBPU_POSITION | none | 0x7 |
_INTCON2_RBPU_SIZE | none | 0x1 |
_INTCON2_RBPU_LENGTH | none | 0x1 |
_INTCON2_RBPU_MASK | none | 0x80 |
INTCON | none | <\077435>INTCON |
INTCON | none | <\077435>INTCON |
_INTCON_RBIF_POSN | none | 0x0 |
_INTCON_RBIF_POSITION | none | 0x0 |
_INTCON_RBIF_SIZE | none | 0x1 |
_INTCON_RBIF_LENGTH | none | 0x1 |
_INTCON_RBIF_MASK | none | 0x1 |
_INTCON_INT0IF_POSN | none | 0x1 |
_INTCON_INT0IF_POSITION | none | 0x1 |
_INTCON_INT0IF_SIZE | none | 0x1 |
_INTCON_INT0IF_LENGTH | none | 0x1 |
_INTCON_INT0IF_MASK | none | 0x2 |
_INTCON_TMR0IF_POSN | none | 0x2 |
_INTCON_TMR0IF_POSITION | none | 0x2 |
_INTCON_TMR0IF_SIZE | none | 0x1 |
_INTCON_TMR0IF_LENGTH | none | 0x1 |
_INTCON_TMR0IF_MASK | none | 0x4 |
_INTCON_RBIE_POSN | none | 0x3 |
_INTCON_RBIE_POSITION | none | 0x3 |
_INTCON_RBIE_SIZE | none | 0x1 |
_INTCON_RBIE_LENGTH | none | 0x1 |
_INTCON_RBIE_MASK | none | 0x8 |
_INTCON_INT0IE_POSN | none | 0x4 |
_INTCON_INT0IE_POSITION | none | 0x4 |
_INTCON_INT0IE_SIZE | none | 0x1 |
_INTCON_INT0IE_LENGTH | none | 0x1 |
_INTCON_INT0IE_MASK | none | 0x10 |
_INTCON_TMR0IE_POSN | none | 0x5 |
_INTCON_TMR0IE_POSITION | none | 0x5 |
_INTCON_TMR0IE_SIZE | none | 0x1 |
_INTCON_TMR0IE_LENGTH | none | 0x1 |
_INTCON_TMR0IE_MASK | none | 0x20 |
_INTCON_PEIE_GIEL_POSN | none | 0x6 |
_INTCON_PEIE_GIEL_POSITION | none | 0x6 |
_INTCON_PEIE_GIEL_SIZE | none | 0x1 |
_INTCON_PEIE_GIEL_LENGTH | none | 0x1 |
_INTCON_PEIE_GIEL_MASK | none | 0x40 |
_INTCON_GIE_GIEH_POSN | none | 0x7 |
_INTCON_GIE_GIEH_POSITION | none | 0x7 |
_INTCON_GIE_GIEH_SIZE | none | 0x1 |
_INTCON_GIE_GIEH_LENGTH | none | 0x1 |
_INTCON_GIE_GIEH_MASK | none | 0x80 |
_INTCON_INT0F_POSN | none | 0x1 |
_INTCON_INT0F_POSITION | none | 0x1 |
_INTCON_INT0F_SIZE | none | 0x1 |
_INTCON_INT0F_LENGTH | none | 0x1 |
_INTCON_INT0F_MASK | none | 0x2 |
_INTCON_T0IF_POSN | none | 0x2 |
_INTCON_T0IF_POSITION | none | 0x2 |
_INTCON_T0IF_SIZE | none | 0x1 |
_INTCON_T0IF_LENGTH | none | 0x1 |
_INTCON_T0IF_MASK | none | 0x4 |
_INTCON_INT0E_POSN | none | 0x4 |
_INTCON_INT0E_POSITION | none | 0x4 |
_INTCON_INT0E_SIZE | none | 0x1 |
_INTCON_INT0E_LENGTH | none | 0x1 |
_INTCON_INT0E_MASK | none | 0x10 |
_INTCON_T0IE_POSN | none | 0x5 |
_INTCON_T0IE_POSITION | none | 0x5 |
_INTCON_T0IE_SIZE | none | 0x1 |
_INTCON_T0IE_LENGTH | none | 0x1 |
_INTCON_T0IE_MASK | none | 0x20 |
_INTCON_PEIE_POSN | none | 0x6 |
_INTCON_PEIE_POSITION | none | 0x6 |
_INTCON_PEIE_SIZE | none | 0x1 |
_INTCON_PEIE_LENGTH | none | 0x1 |
_INTCON_PEIE_MASK | none | 0x40 |
_INTCON_GIE_POSN | none | 0x7 |
_INTCON_GIE_POSITION | none | 0x7 |
_INTCON_GIE_SIZE | none | 0x1 |
_INTCON_GIE_LENGTH | none | 0x1 |
_INTCON_GIE_MASK | none | 0x80 |
_INTCON_GIEL_POSN | none | 0x6 |
_INTCON_GIEL_POSITION | none | 0x6 |
_INTCON_GIEL_SIZE | none | 0x1 |
_INTCON_GIEL_LENGTH | none | 0x1 |
_INTCON_GIEL_MASK | none | 0x40 |
_INTCON_GIEH_POSN | none | 0x7 |
_INTCON_GIEH_POSITION | none | 0x7 |
_INTCON_GIEH_SIZE | none | 0x1 |
_INTCON_GIEH_LENGTH | none | 0x1 |
_INTCON_GIEH_MASK | none | 0x80 |
_INTCON1_RBIF_POSN | none | 0x0 |
_INTCON1_RBIF_POSITION | none | 0x0 |
_INTCON1_RBIF_SIZE | none | 0x1 |
_INTCON1_RBIF_LENGTH | none | 0x1 |
_INTCON1_RBIF_MASK | none | 0x1 |
_INTCON1_INT0IF_POSN | none | 0x1 |
_INTCON1_INT0IF_POSITION | none | 0x1 |
_INTCON1_INT0IF_SIZE | none | 0x1 |
_INTCON1_INT0IF_LENGTH | none | 0x1 |
_INTCON1_INT0IF_MASK | none | 0x2 |
_INTCON1_TMR0IF_POSN | none | 0x2 |
_INTCON1_TMR0IF_POSITION | none | 0x2 |
_INTCON1_TMR0IF_SIZE | none | 0x1 |
_INTCON1_TMR0IF_LENGTH | none | 0x1 |
_INTCON1_TMR0IF_MASK | none | 0x4 |
_INTCON1_RBIE_POSN | none | 0x3 |
_INTCON1_RBIE_POSITION | none | 0x3 |
_INTCON1_RBIE_SIZE | none | 0x1 |
_INTCON1_RBIE_LENGTH | none | 0x1 |
_INTCON1_RBIE_MASK | none | 0x8 |
_INTCON1_INT0IE_POSN | none | 0x4 |
_INTCON1_INT0IE_POSITION | none | 0x4 |
_INTCON1_INT0IE_SIZE | none | 0x1 |
_INTCON1_INT0IE_LENGTH | none | 0x1 |
_INTCON1_INT0IE_MASK | none | 0x10 |
_INTCON1_TMR0IE_POSN | none | 0x5 |
_INTCON1_TMR0IE_POSITION | none | 0x5 |
_INTCON1_TMR0IE_SIZE | none | 0x1 |
_INTCON1_TMR0IE_LENGTH | none | 0x1 |
_INTCON1_TMR0IE_MASK | none | 0x20 |
_INTCON1_PEIE_GIEL_POSN | none | 0x6 |
_INTCON1_PEIE_GIEL_POSITION | none | 0x6 |
_INTCON1_PEIE_GIEL_SIZE | none | 0x1 |
_INTCON1_PEIE_GIEL_LENGTH | none | 0x1 |
_INTCON1_PEIE_GIEL_MASK | none | 0x40 |
_INTCON1_GIE_GIEH_POSN | none | 0x7 |
_INTCON1_GIE_GIEH_POSITION | none | 0x7 |
_INTCON1_GIE_GIEH_SIZE | none | 0x1 |
_INTCON1_GIE_GIEH_LENGTH | none | 0x1 |
_INTCON1_GIE_GIEH_MASK | none | 0x80 |
_INTCON1_INT0F_POSN | none | 0x1 |
_INTCON1_INT0F_POSITION | none | 0x1 |
_INTCON1_INT0F_SIZE | none | 0x1 |
_INTCON1_INT0F_LENGTH | none | 0x1 |
_INTCON1_INT0F_MASK | none | 0x2 |
_INTCON1_T0IF_POSN | none | 0x2 |
_INTCON1_T0IF_POSITION | none | 0x2 |
_INTCON1_T0IF_SIZE | none | 0x1 |
_INTCON1_T0IF_LENGTH | none | 0x1 |
_INTCON1_T0IF_MASK | none | 0x4 |
_INTCON1_INT0E_POSN | none | 0x4 |
_INTCON1_INT0E_POSITION | none | 0x4 |
_INTCON1_INT0E_SIZE | none | 0x1 |
_INTCON1_INT0E_LENGTH | none | 0x1 |
_INTCON1_INT0E_MASK | none | 0x10 |
_INTCON1_T0IE_POSN | none | 0x5 |
_INTCON1_T0IE_POSITION | none | 0x5 |
_INTCON1_T0IE_SIZE | none | 0x1 |
_INTCON1_T0IE_LENGTH | none | 0x1 |
_INTCON1_T0IE_MASK | none | 0x20 |
_INTCON1_PEIE_POSN | none | 0x6 |
_INTCON1_PEIE_POSITION | none | 0x6 |
_INTCON1_PEIE_SIZE | none | 0x1 |
_INTCON1_PEIE_LENGTH | none | 0x1 |
_INTCON1_PEIE_MASK | none | 0x40 |
_INTCON1_GIE_POSN | none | 0x7 |
_INTCON1_GIE_POSITION | none | 0x7 |
_INTCON1_GIE_SIZE | none | 0x1 |
_INTCON1_GIE_LENGTH | none | 0x1 |
_INTCON1_GIE_MASK | none | 0x80 |
_INTCON1_GIEL_POSN | none | 0x6 |
_INTCON1_GIEL_POSITION | none | 0x6 |
_INTCON1_GIEL_SIZE | none | 0x1 |
_INTCON1_GIEL_LENGTH | none | 0x1 |
_INTCON1_GIEL_MASK | none | 0x40 |
_INTCON1_GIEH_POSN | none | 0x7 |
_INTCON1_GIEH_POSITION | none | 0x7 |
_INTCON1_GIEH_SIZE | none | 0x1 |
_INTCON1_GIEH_LENGTH | none | 0x1 |
_INTCON1_GIEH_MASK | none | 0x80 |
PROD | none | <\077435>PROD |
PROD | none | <\077435>PROD |
PRODL | none | <\077435>PRODL |
PRODL | none | <\077435>PRODL |
PRODH | none | <\077435>PRODH |
PRODH | none | <\077435>PRODH |
TABLAT | none | <\077435>TABLAT |
TABLAT | none | <\077435>TABLAT |
TBLPTR | none | <\077435>TBLPTR |
TBLPTR | none | <\077435>TBLPTR |
TBLPTRL | none | <\077435>TBLPTRL |
TBLPTRL | none | <\077435>TBLPTRL |
TBLPTRH | none | <\077435>TBLPTRH |
TBLPTRH | none | <\077435>TBLPTRH |
TBLPTRU | none | <\077435>TBLPTRU |
TBLPTRU | none | <\077435>TBLPTRU |
PCLAT | none | <\077435>PCLAT |
PCLAT | none | <\077435>PCLAT |
PCL | none | <\077435>PCL |
PCL | none | <\077435>PCL |
PCLATH | none | <\077435>PCLATH |
PCLATH | none | <\077435>PCLATH |
PCLATU | none | <\077435>PCLATU |
PCLATU | none | <\077435>PCLATU |
STKPTR | none | <\077435>STKPTR |
STKPTR | none | <\077435>STKPTR |
STKPTR | none | <\077435>STKPTR |
_STKPTR_STKPTR_POSN | none | 0x0 |
_STKPTR_STKPTR_POSITION | none | 0x0 |
_STKPTR_STKPTR_SIZE | none | 0x5 |
_STKPTR_STKPTR_LENGTH | none | 0x5 |
_STKPTR_STKPTR_MASK | none | 0x1F |
_STKPTR_STKUNF_POSN | none | 0x6 |
_STKPTR_STKUNF_POSITION | none | 0x6 |
_STKPTR_STKUNF_SIZE | none | 0x1 |
_STKPTR_STKUNF_LENGTH | none | 0x1 |
_STKPTR_STKUNF_MASK | none | 0x40 |
_STKPTR_STKFUL_POSN | none | 0x7 |
_STKPTR_STKFUL_POSITION | none | 0x7 |
_STKPTR_STKFUL_SIZE | none | 0x1 |
_STKPTR_STKFUL_LENGTH | none | 0x1 |
_STKPTR_STKFUL_MASK | none | 0x80 |
_STKPTR_STKPTR0_POSN | none | 0x0 |
_STKPTR_STKPTR0_POSITION | none | 0x0 |
_STKPTR_STKPTR0_SIZE | none | 0x1 |
_STKPTR_STKPTR0_LENGTH | none | 0x1 |
_STKPTR_STKPTR0_MASK | none | 0x1 |
_STKPTR_STKPTR1_POSN | none | 0x1 |
_STKPTR_STKPTR1_POSITION | none | 0x1 |
_STKPTR_STKPTR1_SIZE | none | 0x1 |
_STKPTR_STKPTR1_LENGTH | none | 0x1 |
_STKPTR_STKPTR1_MASK | none | 0x2 |
_STKPTR_STKPTR2_POSN | none | 0x2 |
_STKPTR_STKPTR2_POSITION | none | 0x2 |
_STKPTR_STKPTR2_SIZE | none | 0x1 |
_STKPTR_STKPTR2_LENGTH | none | 0x1 |
_STKPTR_STKPTR2_MASK | none | 0x4 |
_STKPTR_STKPTR3_POSN | none | 0x3 |
_STKPTR_STKPTR3_POSITION | none | 0x3 |
_STKPTR_STKPTR3_SIZE | none | 0x1 |
_STKPTR_STKPTR3_LENGTH | none | 0x1 |
_STKPTR_STKPTR3_MASK | none | 0x8 |
_STKPTR_STKPTR4_POSN | none | 0x4 |
_STKPTR_STKPTR4_POSITION | none | 0x4 |
_STKPTR_STKPTR4_SIZE | none | 0x1 |
_STKPTR_STKPTR4_LENGTH | none | 0x1 |
_STKPTR_STKPTR4_MASK | none | 0x10 |
_STKPTR_STKOVF_POSN | none | 0x7 |
_STKPTR_STKOVF_POSITION | none | 0x7 |
_STKPTR_STKOVF_SIZE | none | 0x1 |
_STKPTR_STKOVF_LENGTH | none | 0x1 |
_STKPTR_STKOVF_MASK | none | 0x80 |
_STKPTR_SP0_POSN | none | 0x0 |
_STKPTR_SP0_POSITION | none | 0x0 |
_STKPTR_SP0_SIZE | none | 0x1 |
_STKPTR_SP0_LENGTH | none | 0x1 |
_STKPTR_SP0_MASK | none | 0x1 |
_STKPTR_SP1_POSN | none | 0x1 |
_STKPTR_SP1_POSITION | none | 0x1 |
_STKPTR_SP1_SIZE | none | 0x1 |
_STKPTR_SP1_LENGTH | none | 0x1 |
_STKPTR_SP1_MASK | none | 0x2 |
_STKPTR_SP2_POSN | none | 0x2 |
_STKPTR_SP2_POSITION | none | 0x2 |
_STKPTR_SP2_SIZE | none | 0x1 |
_STKPTR_SP2_LENGTH | none | 0x1 |
_STKPTR_SP2_MASK | none | 0x4 |
_STKPTR_SP3_POSN | none | 0x3 |
_STKPTR_SP3_POSITION | none | 0x3 |
_STKPTR_SP3_SIZE | none | 0x1 |
_STKPTR_SP3_LENGTH | none | 0x1 |
_STKPTR_SP3_MASK | none | 0x8 |
_STKPTR_SP4_POSN | none | 0x4 |
_STKPTR_SP4_POSITION | none | 0x4 |
_STKPTR_SP4_SIZE | none | 0x1 |
_STKPTR_SP4_LENGTH | none | 0x1 |
_STKPTR_SP4_MASK | none | 0x10 |
TOS | none | <\077435>TOS |
TOS | none | <\077435>TOS |
TOSL | none | <\077435>TOSL |
TOSL | none | <\077435>TOSL |
TOSH | none | <\077435>TOSH |
TOSH | none | <\077435>TOSH |
TOSU | none | <\077435>TOSU |
TOSU | none | <\077435>TOSU |
_DEPRECATED | none | __attribute__((__deprecated__)) |
BANKMASK | 1 | ((<0>)&0FFh) |
PORTH | none | <\077435>PORTH |
A16_bit | none | BANKMASK(PORTH), 0 |
PORTH | none | <\077435>PORTH |
A17_bit | none | BANKMASK(PORTH), 1 |
PORTH | none | <\077435>PORTH |
A18_bit | none | BANKMASK(PORTH), 2 |
PORTH | none | <\077435>PORTH |
A19_bit | none | BANKMASK(PORTH), 3 |
SSPCON2 | none | <\077435>SSPCON2 |
ACKDT_bit | none | BANKMASK(SSPCON2), 5 |
SSPCON2 | none | <\077435>SSPCON2 |
ACKEN_bit | none | BANKMASK(SSPCON2), 4 |
SSPCON2 | none | <\077435>SSPCON2 |
ACKSTAT_bit | none | BANKMASK(SSPCON2), 6 |
PORTD | none | <\077435>PORTD |
AD0_bit | none | BANKMASK(PORTD), 0 |
PORTD | none | <\077435>PORTD |
AD00_bit | none | BANKMASK(PORTD), 0 |
PORTD | none | <\077435>PORTD |
AD01_bit | none | BANKMASK(PORTD), 1 |
PORTD | none | <\077435>PORTD |
AD02_bit | none | BANKMASK(PORTD), 2 |
PORTD | none | <\077435>PORTD |
AD03_bit | none | BANKMASK(PORTD), 3 |
PORTD | none | <\077435>PORTD |
AD04_bit | none | BANKMASK(PORTD), 4 |
PORTD | none | <\077435>PORTD |
AD05_bit | none | BANKMASK(PORTD), 5 |
PORTD | none | <\077435>PORTD |
AD06_bit | none | BANKMASK(PORTD), 6 |
PORTD | none | <\077435>PORTD |
AD07_bit | none | BANKMASK(PORTD), 7 |
PORTE | none | <\077435>PORTE |
AD08_bit | none | BANKMASK(PORTE), 0 |
PORTE | none | <\077435>PORTE |
AD09_bit | none | BANKMASK(PORTE), 1 |
PORTD | none | <\077435>PORTD |
AD1_bit | none | BANKMASK(PORTD), 1 |
PORTE | none | <\077435>PORTE |
AD10_bit | none | BANKMASK(PORTE), 2 |
PORTE | none | <\077435>PORTE |
AD11_bit | none | BANKMASK(PORTE), 3 |
PORTE | none | <\077435>PORTE |
AD12_bit | none | BANKMASK(PORTE), 4 |
PORTE | none | <\077435>PORTE |
AD13_bit | none | BANKMASK(PORTE), 5 |
PORTE | none | <\077435>PORTE |
AD14_bit | none | BANKMASK(PORTE), 6 |
PORTE | none | <\077435>PORTE |
AD15_bit | none | BANKMASK(PORTE), 7 |
PORTH | none | <\077435>PORTH |
AD16_bit | none | BANKMASK(PORTH), 0 |
PORTH | none | <\077435>PORTH |
AD17_bit | none | BANKMASK(PORTH), 1 |
PORTH | none | <\077435>PORTH |
AD18_bit | none | BANKMASK(PORTH), 2 |
PORTH | none | <\077435>PORTH |
AD19_bit | none | BANKMASK(PORTH), 3 |
PORTD | none | <\077435>PORTD |
AD2_bit | none | BANKMASK(PORTD), 2 |
PORTD | none | <\077435>PORTD |
AD3_bit | none | BANKMASK(PORTD), 3 |
PORTD | none | <\077435>PORTD |
AD4_bit | none | BANKMASK(PORTD), 4 |
PORTD | none | <\077435>PORTD |
AD5_bit | none | BANKMASK(PORTD), 5 |
PORTD | none | <\077435>PORTD |
AD6_bit | none | BANKMASK(PORTD), 6 |
PORTD | none | <\077435>PORTD |
AD7_bit | none | BANKMASK(PORTD), 7 |
PORTE | none | <\077435>PORTE |
AD8_bit | none | BANKMASK(PORTE), 0 |
PORTE | none | <\077435>PORTE |
AD9_bit | none | BANKMASK(PORTE), 1 |
ADCON2 | none | <\077435>ADCON2 |
ADCS0_bit | none | BANKMASK(ADCON2), 0 |
ADCON2 | none | <\077435>ADCON2 |
ADCS1_bit | none | BANKMASK(ADCON2), 1 |
ADCON2 | none | <\077435>ADCON2 |
ADCS2_bit | none | BANKMASK(ADCON2), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
ADDEN_bit | none | BANKMASK(RCSTA1), 3 |
RCSTA1 | none | <\077435>RCSTA1 |
ADDEN1_bit | none | BANKMASK(RCSTA1), 3 |
RCSTA2 | none | <\077435>RCSTA2 |
ADDEN2_bit | none | BANKMASK(RCSTA2), 3 |
ADCON2 | none | <\077435>ADCON2 |
ADFM_bit | none | BANKMASK(ADCON2), 7 |
PIE1 | none | <\077435>PIE1 |
ADIE_bit | none | BANKMASK(PIE1), 6 |
PIR1 | none | <\077435>PIR1 |
ADIF_bit | none | BANKMASK(PIR1), 6 |
IPR1 | none | <\077435>IPR1 |
ADIP_bit | none | BANKMASK(IPR1), 6 |
ADCON0 | none | <\077435>ADCON0 |
ADON_bit | none | BANKMASK(ADCON0), 0 |
PORTJ | none | <\077435>PORTJ |
ALE_bit | none | BANKMASK(PORTJ), 0 |
PORTA | none | <\077435>PORTA |
AN0_bit | none | BANKMASK(PORTA), 0 |
PORTA | none | <\077435>PORTA |
AN1_bit | none | BANKMASK(PORTA), 1 |
PORTF | none | <\077435>PORTF |
AN10_bit | none | BANKMASK(PORTF), 5 |
PORTF | none | <\077435>PORTF |
AN11_bit | none | BANKMASK(PORTF), 6 |
PORTH | none | <\077435>PORTH |
AN12_bit | none | BANKMASK(PORTH), 4 |
PORTH | none | <\077435>PORTH |
AN13_bit | none | BANKMASK(PORTH), 5 |
PORTH | none | <\077435>PORTH |
AN14_bit | none | BANKMASK(PORTH), 6 |
PORTH | none | <\077435>PORTH |
AN15_bit | none | BANKMASK(PORTH), 7 |
PORTA | none | <\077435>PORTA |
AN2_bit | none | BANKMASK(PORTA), 2 |
PORTA | none | <\077435>PORTA |
AN3_bit | none | BANKMASK(PORTA), 3 |
PORTA | none | <\077435>PORTA |
AN4_bit | none | BANKMASK(PORTA), 5 |
PORTF | none | <\077435>PORTF |
AN5_bit | none | BANKMASK(PORTF), 0 |
PORTF | none | <\077435>PORTF |
AN6_bit | none | BANKMASK(PORTF), 1 |
PORTF | none | <\077435>PORTF |
AN7_bit | none | BANKMASK(PORTF), 2 |
PORTF | none | <\077435>PORTF |
AN8_bit | none | BANKMASK(PORTF), 3 |
PORTF | none | <\077435>PORTF |
AN9_bit | none | BANKMASK(PORTF), 4 |
PORTJ | none | <\077435>PORTJ |
BA0_bit | none | BANKMASK(PORTJ), 4 |
PIE2 | none | <\077435>PIE2 |
BCLIE_bit | none | BANKMASK(PIE2), 3 |
PIR2 | none | <\077435>PIR2 |
BCLIF_bit | none | BANKMASK(PIR2), 3 |
IPR2 | none | <\077435>IPR2 |
BCLIP_bit | none | BANKMASK(IPR2), 3 |
SSPSTAT | none | <\077435>SSPSTAT |
BF_bit | none | BANKMASK(SSPSTAT), 0 |
LVDCON | none | <\077435>LVDCON |
BGST_bit | none | BANKMASK(LVDCON), 5 |
RCON | none | <\077435>RCON |
BOR_bit | none | BANKMASK(RCON), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
BRGH_bit | none | BANKMASK(TXSTA1), 2 |
TXSTA1 | none | <\077435>TXSTA1 |
BRGH1_bit | none | BANKMASK(TXSTA1), 2 |
TXSTA2 | none | <\077435>TXSTA2 |
BRGH2_bit | none | BANKMASK(TXSTA2), 2 |
CMCON | none | <\077435>CMCON |
C1INV_bit | none | BANKMASK(CMCON), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
CMCON | none | <\077435>CMCON |
C1OUT_bit | none | BANKMASK(CMCON), 6 |
PORTF | none | <\077435>PORTF |
C1OUTF_bit | none | BANKMASK(PORTF), 2 |
CMCON | none | <\077435>CMCON |
C2INV_bit | none | BANKMASK(CMCON), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
CMCON | none | <\077435>CMCON |
C2OUT_bit | none | BANKMASK(CMCON), 7 |
PORTF | none | <\077435>PORTF |
C2OUTF_bit | none | BANKMASK(PORTF), 1 |
PORTG | none | <\077435>PORTG |
C3OUTG_bit | none | BANKMASK(PORTG), 1 |
STATUS | none | <\077435>STATUS |
CARRY_bit | none | BANKMASK(STATUS), 0 |
PORTC | none | <\077435>PORTC |
CCP1_bit | none | BANKMASK(PORTC), 2 |
PORTE | none | <\077435>PORTE |
CCP10_bit | none | BANKMASK(PORTE), 2 |
PIE1 | none | <\077435>PIE1 |
CCP1IE_bit | none | BANKMASK(PIE1), 2 |
PIR1 | none | <\077435>PIR1 |
CCP1IF_bit | none | BANKMASK(PIR1), 2 |
IPR1 | none | <\077435>IPR1 |
CCP1IP_bit | none | BANKMASK(IPR1), 2 |
CCP1CON | none | <\077435>CCP1CON |
CCP1M0_bit | none | BANKMASK(CCP1CON), 0 |
CCP1CON | none | <\077435>CCP1CON |
CCP1M1_bit | none | BANKMASK(CCP1CON), 1 |
CCP1CON | none | <\077435>CCP1CON |
CCP1M2_bit | none | BANKMASK(CCP1CON), 2 |
CCP1CON | none | <\077435>CCP1CON |
CCP1M3_bit | none | BANKMASK(CCP1CON), 3 |
CCP1CON | none | <\077435>CCP1CON |
CCP1X_bit | none | BANKMASK(CCP1CON), 5 |
CCP1CON | none | <\077435>CCP1CON |
CCP1Y_bit | none | BANKMASK(CCP1CON), 4 |
PORTE | none | <\077435>PORTE |
CCP2C_bit | none | BANKMASK(PORTE), 7 |
PORTE | none | <\077435>PORTE |
CCP2E_bit | none | BANKMASK(PORTE), 7 |
PIE2 | none | <\077435>PIE2 |
CCP2IE_bit | none | BANKMASK(PIE2), 0 |
PIR2 | none | <\077435>PIR2 |
CCP2IF_bit | none | BANKMASK(PIR2), 0 |
IPR2 | none | <\077435>IPR2 |
CCP2IP_bit | none | BANKMASK(IPR2), 0 |
CCP2CON | none | <\077435>CCP2CON |
CCP2M0_bit | none | BANKMASK(CCP2CON), 0 |
CCP2CON | none | <\077435>CCP2CON |
CCP2M1_bit | none | BANKMASK(CCP2CON), 1 |
CCP2CON | none | <\077435>CCP2CON |
CCP2M2_bit | none | BANKMASK(CCP2CON), 2 |
CCP2CON | none | <\077435>CCP2CON |
CCP2M3_bit | none | BANKMASK(CCP2CON), 3 |
CCP2CON | none | <\077435>CCP2CON |
CCP2X_bit | none | BANKMASK(CCP2CON), 5 |
CCP2CON | none | <\077435>CCP2CON |
CCP2Y_bit | none | BANKMASK(CCP2CON), 4 |
PORTB | none | <\077435>PORTB |
CCP2_PA2_bit | none | BANKMASK(PORTB), 3 |
PORTG | none | <\077435>PORTG |
CCP3_bit | none | BANKMASK(PORTG), 0 |
PIE3 | none | <\077435>PIE3 |
CCP3IE_bit | none | BANKMASK(PIE3), 0 |
PIR3 | none | <\077435>PIR3 |
CCP3IF_bit | none | BANKMASK(PIR3), 0 |
IPR3 | none | <\077435>IPR3 |
CCP3IP_bit | none | BANKMASK(IPR3), 0 |
CCP3CON | none | <\077435>CCP3CON |
CCP3M0_bit | none | BANKMASK(CCP3CON), 0 |
CCP3CON | none | <\077435>CCP3CON |
CCP3M1_bit | none | BANKMASK(CCP3CON), 1 |
CCP3CON | none | <\077435>CCP3CON |
CCP3M2_bit | none | BANKMASK(CCP3CON), 2 |
CCP3CON | none | <\077435>CCP3CON |
CCP3M3_bit | none | BANKMASK(CCP3CON), 3 |
PORTG | none | <\077435>PORTG |
CCP4_bit | none | BANKMASK(PORTG), 3 |
PIE3 | none | <\077435>PIE3 |
CCP4IE_bit | none | BANKMASK(PIE3), 1 |
PIR3 | none | <\077435>PIR3 |
CCP4IF_bit | none | BANKMASK(PIR3), 1 |
IPR3 | none | <\077435>IPR3 |
CCP4IP_bit | none | BANKMASK(IPR3), 1 |
CCP4CON | none | <\077435>CCP4CON |
CCP4M0_bit | none | BANKMASK(CCP4CON), 0 |
CCP4CON | none | <\077435>CCP4CON |
CCP4M1_bit | none | BANKMASK(CCP4CON), 1 |
CCP4CON | none | <\077435>CCP4CON |
CCP4M2_bit | none | BANKMASK(CCP4CON), 2 |
CCP4CON | none | <\077435>CCP4CON |
CCP4M3_bit | none | BANKMASK(CCP4CON), 3 |
PORTG | none | <\077435>PORTG |
CCP5_bit | none | BANKMASK(PORTG), 4 |
PIE3 | none | <\077435>PIE3 |
CCP5IE_bit | none | BANKMASK(PIE3), 2 |
PIR3 | none | <\077435>PIR3 |
CCP5IF_bit | none | BANKMASK(PIR3), 2 |
IPR3 | none | <\077435>IPR3 |
CCP5IP_bit | none | BANKMASK(IPR3), 2 |
CCP5CON | none | <\077435>CCP5CON |
CCP5M0_bit | none | BANKMASK(CCP5CON), 0 |
CCP5CON | none | <\077435>CCP5CON |
CCP5M1_bit | none | BANKMASK(CCP5CON), 1 |
CCP5CON | none | <\077435>CCP5CON |
CCP5M2_bit | none | BANKMASK(CCP5CON), 2 |
CCP5CON | none | <\077435>CCP5CON |
CCP5M3_bit | none | BANKMASK(CCP5CON), 3 |
PORTH | none | <\077435>PORTH |
CCP6_bit | none | BANKMASK(PORTH), 7 |
PORTE | none | <\077435>PORTE |
CCP6E_bit | none | BANKMASK(PORTE), 6 |
PORTH | none | <\077435>PORTH |
CCP7_bit | none | BANKMASK(PORTH), 6 |
PORTE | none | <\077435>PORTE |
CCP7E_bit | none | BANKMASK(PORTE), 5 |
PORTH | none | <\077435>PORTH |
CCP8_bit | none | BANKMASK(PORTH), 5 |
PORTE | none | <\077435>PORTE |
CCP8E_bit | none | BANKMASK(PORTE), 4 |
PORTH | none | <\077435>PORTH |
CCP9_bit | none | BANKMASK(PORTH), 4 |
PORTE | none | <\077435>PORTE |
CCP9E_bit | none | BANKMASK(PORTE), 3 |
PORTJ | none | <\077435>PORTJ |
CE_bit | none | BANKMASK(PORTJ), 5 |
EECON1 | none | <\077435>EECON1 |
CFGS_bit | none | BANKMASK(EECON1), 6 |
ADCON0 | none | <\077435>ADCON0 |
CHS0_bit | none | BANKMASK(ADCON0), 2 |
ADCON0 | none | <\077435>ADCON0 |
CHS1_bit | none | BANKMASK(ADCON0), 3 |
ADCON0 | none | <\077435>ADCON0 |
CHS2_bit | none | BANKMASK(ADCON0), 4 |
ADCON0 | none | <\077435>ADCON0 |
CHS3_bit | none | BANKMASK(ADCON0), 5 |
ADCON1 | none | <\077435>ADCON1 |
CHSN3_bit | none | BANKMASK(ADCON1), 3 |
CMCON | none | <\077435>CMCON |
CIS_bit | none | BANKMASK(CMCON), 3 |
PORTC | none | <\077435>PORTC |
CK_bit | none | BANKMASK(PORTC), 6 |
PORTG | none | <\077435>PORTG |
CK2_bit | none | BANKMASK(PORTG), 1 |
SSPSTAT | none | <\077435>SSPSTAT |
CKE_bit | none | BANKMASK(SSPSTAT), 6 |
SSPCON1 | none | <\077435>SSPCON1 |
CKP_bit | none | BANKMASK(SSPCON1), 4 |
PORTA | none | <\077435>PORTA |
CLKO_bit | none | BANKMASK(PORTA), 6 |
CMCON | none | <\077435>CMCON |
CM0_bit | none | BANKMASK(CMCON), 0 |
CMCON | none | <\077435>CMCON |
CM1_bit | none | BANKMASK(CMCON), 1 |
CMCON | none | <\077435>CMCON |
CM2_bit | none | BANKMASK(CMCON), 2 |
CMCON | none | <\077435>CMCON |
CMEN0_bit | none | BANKMASK(CMCON), 0 |
CMCON | none | <\077435>CMCON |
CMEN1_bit | none | BANKMASK(CMCON), 1 |
CMCON | none | <\077435>CMCON |
CMEN2_bit | none | BANKMASK(CMCON), 2 |
PIE2 | none | <\077435>PIE2 |
CMIE_bit | none | BANKMASK(PIE2), 6 |
PIR2 | none | <\077435>PIR2 |
CMIF_bit | none | BANKMASK(PIR2), 6 |
IPR2 | none | <\077435>IPR2 |
CMIP_bit | none | BANKMASK(IPR2), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
CREN_bit | none | BANKMASK(RCSTA1), 4 |
RCSTA1 | none | <\077435>RCSTA1 |
CREN1_bit | none | BANKMASK(RCSTA1), 4 |
RCSTA2 | none | <\077435>RCSTA2 |
CREN2_bit | none | BANKMASK(RCSTA2), 4 |
PORTE | none | <\077435>PORTE |
CS_bit | none | BANKMASK(PORTE), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
CSRC_bit | none | BANKMASK(TXSTA1), 7 |
TXSTA1 | none | <\077435>TXSTA1 |
CSRC1_bit | none | BANKMASK(TXSTA1), 7 |
TXSTA2 | none | <\077435>TXSTA2 |
CSRC2_bit | none | BANKMASK(TXSTA2), 7 |
CVRCON | none | <\077435>CVRCON |
CVR0_bit | none | BANKMASK(CVRCON), 0 |
CVRCON | none | <\077435>CVRCON |
CVR1_bit | none | BANKMASK(CVRCON), 1 |
CVRCON | none | <\077435>CVRCON |
CVR2_bit | none | BANKMASK(CVRCON), 2 |
CVRCON | none | <\077435>CVRCON |
CVR3_bit | none | BANKMASK(CVRCON), 3 |
CVRCON | none | <\077435>CVRCON |
CVREN_bit | none | BANKMASK(CVRCON), 7 |
CVRCON | none | <\077435>CVRCON |
CVROE_bit | none | BANKMASK(CVRCON), 6 |
CVRCON | none | <\077435>CVRCON |
CVROEN_bit | none | BANKMASK(CVRCON), 6 |
CVRCON | none | <\077435>CVRCON |
CVRR_bit | none | BANKMASK(CVRCON), 5 |
CVRCON | none | <\077435>CVRCON |
CVRSS_bit | none | BANKMASK(CVRCON), 4 |
SSPSTAT | none | <\077435>SSPSTAT |
DA_bit | none | BANKMASK(SSPSTAT), 5 |
SSPSTAT | none | <\077435>SSPSTAT |
DATA_ADDRESS_bit | none | BANKMASK(SSPSTAT), 5 |
STATUS | none | <\077435>STATUS |
DC_bit | none | BANKMASK(STATUS), 1 |
CCP1CON | none | <\077435>CCP1CON |
DC1B0_bit | none | BANKMASK(CCP1CON), 4 |
CCP1CON | none | <\077435>CCP1CON |
DC1B1_bit | none | BANKMASK(CCP1CON), 5 |
CCP2CON | none | <\077435>CCP2CON |
DC2B0_bit | none | BANKMASK(CCP2CON), 4 |
CCP2CON | none | <\077435>CCP2CON |
DC2B1_bit | none | BANKMASK(CCP2CON), 5 |
CCP3CON | none | <\077435>CCP3CON |
DC3B0_bit | none | BANKMASK(CCP3CON), 4 |
CCP3CON | none | <\077435>CCP3CON |
DC3B1_bit | none | BANKMASK(CCP3CON), 5 |
CCP4CON | none | <\077435>CCP4CON |
DC4B0_bit | none | BANKMASK(CCP4CON), 4 |
CCP4CON | none | <\077435>CCP4CON |
DC4B1_bit | none | BANKMASK(CCP4CON), 5 |
CCP5CON | none | <\077435>CCP5CON |
DC5B0_bit | none | BANKMASK(CCP5CON), 4 |
CCP5CON | none | <\077435>CCP5CON |
DC5B1_bit | none | BANKMASK(CCP5CON), 5 |
CCP1CON | none | <\077435>CCP1CON |
DCCP1X_bit | none | BANKMASK(CCP1CON), 5 |
CCP1CON | none | <\077435>CCP1CON |
DCCP1Y_bit | none | BANKMASK(CCP1CON), 4 |
CCP2CON | none | <\077435>CCP2CON |
DCCP2X_bit | none | BANKMASK(CCP2CON), 5 |
CCP2CON | none | <\077435>CCP2CON |
DCCP2Y_bit | none | BANKMASK(CCP2CON), 4 |
CCP3CON | none | <\077435>CCP3CON |
DCCP3X_bit | none | BANKMASK(CCP3CON), 5 |
CCP3CON | none | <\077435>CCP3CON |
DCCP3Y_bit | none | BANKMASK(CCP3CON), 4 |
CCP4CON | none | <\077435>CCP4CON |
DCCP4X_bit | none | BANKMASK(CCP4CON), 5 |
CCP4CON | none | <\077435>CCP4CON |
DCCP4Y_bit | none | BANKMASK(CCP4CON), 4 |
CCP5CON | none | <\077435>CCP5CON |
DCCP5X_bit | none | BANKMASK(CCP5CON), 5 |
CCP5CON | none | <\077435>CCP5CON |
DCCP5Y_bit | none | BANKMASK(CCP5CON), 4 |
ADCON0 | none | <\077435>ADCON0 |
DONE_bit | none | BANKMASK(ADCON0), 1 |
PORTC | none | <\077435>PORTC |
DT_bit | none | BANKMASK(PORTC), 7 |
PORTG | none | <\077435>PORTG |
DT2_bit | none | BANKMASK(PORTG), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
D_A_bit | none | BANKMASK(SSPSTAT), 5 |
SSPSTAT | none | <\077435>SSPSTAT |
D_NOT_A_bit | none | BANKMASK(SSPSTAT), 5 |
SSPSTAT | none | <\077435>SSPSTAT |
D_nA_bit | none | BANKMASK(SSPSTAT), 5 |
MEMCON | none | <\077435>MEMCON |
EBDIS_bit | none | BANKMASK(MEMCON), 7 |
EECON1 | none | <\077435>EECON1 |
EEFS_bit | none | BANKMASK(EECON1), 6 |
PIE2 | none | <\077435>PIE2 |
EEIE_bit | none | BANKMASK(PIE2), 4 |
PIR2 | none | <\077435>PIR2 |
EEIF_bit | none | BANKMASK(PIR2), 4 |
IPR2 | none | <\077435>IPR2 |
EEIP_bit | none | BANKMASK(IPR2), 4 |
EECON1 | none | <\077435>EECON1 |
EEPGD_bit | none | BANKMASK(EECON1), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
FERR_bit | none | BANKMASK(RCSTA1), 2 |
RCSTA1 | none | <\077435>RCSTA1 |
FERR1_bit | none | BANKMASK(RCSTA1), 2 |
RCSTA2 | none | <\077435>RCSTA2 |
FERR2_bit | none | BANKMASK(RCSTA2), 2 |
EECON1 | none | <\077435>EECON1 |
FREE_bit | none | BANKMASK(EECON1), 4 |
SSPCON2 | none | <\077435>SSPCON2 |
GCEN_bit | none | BANKMASK(SSPCON2), 7 |
INTCON | none | <\077435>INTCON |
GIE_bit | none | BANKMASK(INTCON), 7 |
INTCON | none | <\077435>INTCON |
GIEH_bit | none | BANKMASK(INTCON), 7 |
INTCON | none | <\077435>INTCON |
GIEL_bit | none | BANKMASK(INTCON), 6 |
INTCON | none | <\077435>INTCON |
GIE_GIEH_bit | none | BANKMASK(INTCON), 7 |
ADCON0 | none | <\077435>ADCON0 |
GO_bit | none | BANKMASK(ADCON0), 1 |
ADCON0 | none | <\077435>ADCON0 |
GODONE_bit | none | BANKMASK(ADCON0), 1 |
ADCON0 | none | <\077435>ADCON0 |
GO_DONE_bit | none | BANKMASK(ADCON0), 1 |
ADCON0 | none | <\077435>ADCON0 |
GO_NOT_DONE_bit | none | BANKMASK(ADCON0), 1 |
ADCON0 | none | <\077435>ADCON0 |
GO_nDONE_bit | none | BANKMASK(ADCON0), 1 |
SSPSTAT | none | <\077435>SSPSTAT |
I2C_DAT_bit | none | BANKMASK(SSPSTAT), 5 |
SSPSTAT | none | <\077435>SSPSTAT |
I2C_READ_bit | none | BANKMASK(SSPSTAT), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
I2C_START_bit | none | BANKMASK(SSPSTAT), 3 |
SSPSTAT | none | <\077435>SSPSTAT |
I2C_STOP_bit | none | BANKMASK(SSPSTAT), 4 |
PSPCON | none | <\077435>PSPCON |
IBF_bit | none | BANKMASK(PSPCON), 7 |
PSPCON | none | <\077435>PSPCON |
IBOV_bit | none | BANKMASK(PSPCON), 5 |
PORTB | none | <\077435>PORTB |
INT0_bit | none | BANKMASK(PORTB), 0 |
INTCON | none | <\077435>INTCON |
INT0E_bit | none | BANKMASK(INTCON), 4 |
INTCON | none | <\077435>INTCON |
INT0F_bit | none | BANKMASK(INTCON), 1 |
INTCON | none | <\077435>INTCON |
INT0IE_bit | none | BANKMASK(INTCON), 4 |
INTCON | none | <\077435>INTCON |
INT0IF_bit | none | BANKMASK(INTCON), 1 |
PORTB | none | <\077435>PORTB |
INT1_bit | none | BANKMASK(PORTB), 1 |
INTCON3 | none | <\077435>INTCON3 |
INT1E_bit | none | BANKMASK(INTCON3), 3 |
INTCON3 | none | <\077435>INTCON3 |
INT1F_bit | none | BANKMASK(INTCON3), 0 |
INTCON3 | none | <\077435>INTCON3 |
INT1IE_bit | none | BANKMASK(INTCON3), 3 |
INTCON3 | none | <\077435>INTCON3 |
INT1IF_bit | none | BANKMASK(INTCON3), 0 |
INTCON3 | none | <\077435>INTCON3 |
INT1IP_bit | none | BANKMASK(INTCON3), 6 |
INTCON3 | none | <\077435>INTCON3 |
INT1P_bit | none | BANKMASK(INTCON3), 6 |
PORTB | none | <\077435>PORTB |
INT2_bit | none | BANKMASK(PORTB), 2 |
INTCON3 | none | <\077435>INTCON3 |
INT2E_bit | none | BANKMASK(INTCON3), 4 |
INTCON3 | none | <\077435>INTCON3 |
INT2F_bit | none | BANKMASK(INTCON3), 1 |
INTCON3 | none | <\077435>INTCON3 |
INT2IE_bit | none | BANKMASK(INTCON3), 4 |
INTCON3 | none | <\077435>INTCON3 |
INT2IF_bit | none | BANKMASK(INTCON3), 1 |
INTCON3 | none | <\077435>INTCON3 |
INT2IP_bit | none | BANKMASK(INTCON3), 7 |
INTCON3 | none | <\077435>INTCON3 |
INT2P_bit | none | BANKMASK(INTCON3), 7 |
PORTB | none | <\077435>PORTB |
INT3_bit | none | BANKMASK(PORTB), 3 |
INTCON3 | none | <\077435>INTCON3 |
INT3E_bit | none | BANKMASK(INTCON3), 5 |
INTCON3 | none | <\077435>INTCON3 |
INT3F_bit | none | BANKMASK(INTCON3), 2 |
INTCON3 | none | <\077435>INTCON3 |
INT3IE_bit | none | BANKMASK(INTCON3), 5 |
INTCON3 | none | <\077435>INTCON3 |
INT3IF_bit | none | BANKMASK(INTCON3), 2 |
INTCON2 | none | <\077435>INTCON2 |
INT3IP_bit | none | BANKMASK(INTCON2), 1 |
INTCON2 | none | <\077435>INTCON2 |
INT3P_bit | none | BANKMASK(INTCON2), 1 |
INTCON2 | none | <\077435>INTCON2 |
INTEDG0_bit | none | BANKMASK(INTCON2), 6 |
INTCON2 | none | <\077435>INTCON2 |
INTEDG1_bit | none | BANKMASK(INTCON2), 5 |
INTCON2 | none | <\077435>INTCON2 |
INTEDG2_bit | none | BANKMASK(INTCON2), 4 |
INTCON2 | none | <\077435>INTCON2 |
INTEDG3_bit | none | BANKMASK(INTCON2), 3 |
RCON | none | <\077435>RCON |
IPEN_bit | none | BANKMASK(RCON), 7 |
LVDCON | none | <\077435>LVDCON |
IRVST_bit | none | BANKMASK(LVDCON), 5 |
PORTB | none | <\077435>PORTB |
KBI0_bit | none | BANKMASK(PORTB), 4 |
PORTB | none | <\077435>PORTB |
KBI1_bit | none | BANKMASK(PORTB), 5 |
PORTB | none | <\077435>PORTB |
KBI2_bit | none | BANKMASK(PORTB), 6 |
PORTB | none | <\077435>PORTB |
KBI3_bit | none | BANKMASK(PORTB), 7 |
LATA | none | <\077435>LATA |
LA0_bit | none | BANKMASK(LATA), 0 |
LATA | none | <\077435>LATA |
LA1_bit | none | BANKMASK(LATA), 1 |
LATA | none | <\077435>LATA |
LA2_bit | none | BANKMASK(LATA), 2 |
LATA | none | <\077435>LATA |
LA3_bit | none | BANKMASK(LATA), 3 |
LATA | none | <\077435>LATA |
LA4_bit | none | BANKMASK(LATA), 4 |
LATA | none | <\077435>LATA |
LA5_bit | none | BANKMASK(LATA), 5 |
LATA | none | <\077435>LATA |
LA6_bit | none | BANKMASK(LATA), 6 |
LATA | none | <\077435>LATA |
LATA0_bit | none | BANKMASK(LATA), 0 |
LATA | none | <\077435>LATA |
LATA1_bit | none | BANKMASK(LATA), 1 |
LATA | none | <\077435>LATA |
LATA2_bit | none | BANKMASK(LATA), 2 |
LATA | none | <\077435>LATA |
LATA3_bit | none | BANKMASK(LATA), 3 |
LATA | none | <\077435>LATA |
LATA4_bit | none | BANKMASK(LATA), 4 |
LATA | none | <\077435>LATA |
LATA5_bit | none | BANKMASK(LATA), 5 |
LATA | none | <\077435>LATA |
LATA6_bit | none | BANKMASK(LATA), 6 |
LATB | none | <\077435>LATB |
LATB0_bit | none | BANKMASK(LATB), 0 |
LATB | none | <\077435>LATB |
LATB1_bit | none | BANKMASK(LATB), 1 |
LATB | none | <\077435>LATB |
LATB2_bit | none | BANKMASK(LATB), 2 |
LATB | none | <\077435>LATB |
LATB3_bit | none | BANKMASK(LATB), 3 |
LATB | none | <\077435>LATB |
LATB4_bit | none | BANKMASK(LATB), 4 |
LATB | none | <\077435>LATB |
LATB5_bit | none | BANKMASK(LATB), 5 |
LATB | none | <\077435>LATB |
LATB6_bit | none | BANKMASK(LATB), 6 |
LATB | none | <\077435>LATB |
LATB7_bit | none | BANKMASK(LATB), 7 |
LATC | none | <\077435>LATC |
LATC0_bit | none | BANKMASK(LATC), 0 |
LATC | none | <\077435>LATC |
LATC1_bit | none | BANKMASK(LATC), 1 |
LATC | none | <\077435>LATC |
LATC2_bit | none | BANKMASK(LATC), 2 |
LATC | none | <\077435>LATC |
LATC3_bit | none | BANKMASK(LATC), 3 |
LATC | none | <\077435>LATC |
LATC4_bit | none | BANKMASK(LATC), 4 |
LATC | none | <\077435>LATC |
LATC5_bit | none | BANKMASK(LATC), 5 |
LATC | none | <\077435>LATC |
LATC6_bit | none | BANKMASK(LATC), 6 |
LATC | none | <\077435>LATC |
LATC7_bit | none | BANKMASK(LATC), 7 |
LATD | none | <\077435>LATD |
LATD0_bit | none | BANKMASK(LATD), 0 |
LATD | none | <\077435>LATD |
LATD1_bit | none | BANKMASK(LATD), 1 |
LATD | none | <\077435>LATD |
LATD2_bit | none | BANKMASK(LATD), 2 |
LATD | none | <\077435>LATD |
LATD3_bit | none | BANKMASK(LATD), 3 |
LATD | none | <\077435>LATD |
LATD4_bit | none | BANKMASK(LATD), 4 |
LATD | none | <\077435>LATD |
LATD5_bit | none | BANKMASK(LATD), 5 |
LATD | none | <\077435>LATD |
LATD6_bit | none | BANKMASK(LATD), 6 |
LATD | none | <\077435>LATD |
LATD7_bit | none | BANKMASK(LATD), 7 |
LATE | none | <\077435>LATE |
LATE0_bit | none | BANKMASK(LATE), 0 |
LATE | none | <\077435>LATE |
LATE1_bit | none | BANKMASK(LATE), 1 |
LATE | none | <\077435>LATE |
LATE2_bit | none | BANKMASK(LATE), 2 |
LATE | none | <\077435>LATE |
LATE3_bit | none | BANKMASK(LATE), 3 |
LATE | none | <\077435>LATE |
LATE4_bit | none | BANKMASK(LATE), 4 |
LATE | none | <\077435>LATE |
LATE5_bit | none | BANKMASK(LATE), 5 |
LATE | none | <\077435>LATE |
LATE6_bit | none | BANKMASK(LATE), 6 |
LATE | none | <\077435>LATE |
LATE7_bit | none | BANKMASK(LATE), 7 |
LATF | none | <\077435>LATF |
LATF0_bit | none | BANKMASK(LATF), 0 |
LATF | none | <\077435>LATF |
LATF1_bit | none | BANKMASK(LATF), 1 |
LATF | none | <\077435>LATF |
LATF2_bit | none | BANKMASK(LATF), 2 |
LATF | none | <\077435>LATF |
LATF3_bit | none | BANKMASK(LATF), 3 |
LATF | none | <\077435>LATF |
LATF4_bit | none | BANKMASK(LATF), 4 |
LATF | none | <\077435>LATF |
LATF5_bit | none | BANKMASK(LATF), 5 |
LATF | none | <\077435>LATF |
LATF6_bit | none | BANKMASK(LATF), 6 |
LATF | none | <\077435>LATF |
LATF7_bit | none | BANKMASK(LATF), 7 |
LATG | none | <\077435>LATG |
LATG0_bit | none | BANKMASK(LATG), 0 |
LATG | none | <\077435>LATG |
LATG1_bit | none | BANKMASK(LATG), 1 |
LATG | none | <\077435>LATG |
LATG2_bit | none | BANKMASK(LATG), 2 |
LATG | none | <\077435>LATG |
LATG3_bit | none | BANKMASK(LATG), 3 |
LATG | none | <\077435>LATG |
LATG4_bit | none | BANKMASK(LATG), 4 |
LATH | none | <\077435>LATH |
LATH0_bit | none | BANKMASK(LATH), 0 |
LATH | none | <\077435>LATH |
LATH1_bit | none | BANKMASK(LATH), 1 |
LATH | none | <\077435>LATH |
LATH2_bit | none | BANKMASK(LATH), 2 |
LATH | none | <\077435>LATH |
LATH3_bit | none | BANKMASK(LATH), 3 |
LATH | none | <\077435>LATH |
LATH4_bit | none | BANKMASK(LATH), 4 |
LATH | none | <\077435>LATH |
LATH5_bit | none | BANKMASK(LATH), 5 |
LATH | none | <\077435>LATH |
LATH6_bit | none | BANKMASK(LATH), 6 |
LATH | none | <\077435>LATH |
LATH7_bit | none | BANKMASK(LATH), 7 |
LATJ | none | <\077435>LATJ |
LATJ0_bit | none | BANKMASK(LATJ), 0 |
LATJ | none | <\077435>LATJ |
LATJ1_bit | none | BANKMASK(LATJ), 1 |
LATJ | none | <\077435>LATJ |
LATJ2_bit | none | BANKMASK(LATJ), 2 |
LATJ | none | <\077435>LATJ |
LATJ3_bit | none | BANKMASK(LATJ), 3 |
LATJ | none | <\077435>LATJ |
LATJ4_bit | none | BANKMASK(LATJ), 4 |
LATJ | none | <\077435>LATJ |
LATJ5_bit | none | BANKMASK(LATJ), 5 |
LATJ | none | <\077435>LATJ |
LATJ6_bit | none | BANKMASK(LATJ), 6 |
LATJ | none | <\077435>LATJ |
LATJ7_bit | none | BANKMASK(LATJ), 7 |
PORTJ | none | <\077435>PORTJ |
LB_bit | none | BANKMASK(PORTJ), 6 |
LATB | none | <\077435>LATB |
LB0_bit | none | BANKMASK(LATB), 0 |
LATB | none | <\077435>LATB |
LB1_bit | none | BANKMASK(LATB), 1 |
LATB | none | <\077435>LATB |
LB2_bit | none | BANKMASK(LATB), 2 |
LATB | none | <\077435>LATB |
LB3_bit | none | BANKMASK(LATB), 3 |
LATB | none | <\077435>LATB |
LB4_bit | none | BANKMASK(LATB), 4 |
LATB | none | <\077435>LATB |
LB5_bit | none | BANKMASK(LATB), 5 |
LATB | none | <\077435>LATB |
LB6_bit | none | BANKMASK(LATB), 6 |
LATB | none | <\077435>LATB |
LB7_bit | none | BANKMASK(LATB), 7 |
LATC | none | <\077435>LATC |
LC0_bit | none | BANKMASK(LATC), 0 |
LATC | none | <\077435>LATC |
LC1_bit | none | BANKMASK(LATC), 1 |
LATC | none | <\077435>LATC |
LC2_bit | none | BANKMASK(LATC), 2 |
LATC | none | <\077435>LATC |
LC3_bit | none | BANKMASK(LATC), 3 |
LATC | none | <\077435>LATC |
LC4_bit | none | BANKMASK(LATC), 4 |
LATC | none | <\077435>LATC |
LC5_bit | none | BANKMASK(LATC), 5 |
LATC | none | <\077435>LATC |
LC6_bit | none | BANKMASK(LATC), 6 |
LATC | none | <\077435>LATC |
LC7_bit | none | BANKMASK(LATC), 7 |
LATD | none | <\077435>LATD |
LD0_bit | none | BANKMASK(LATD), 0 |
LATD | none | <\077435>LATD |
LD1_bit | none | BANKMASK(LATD), 1 |
LATD | none | <\077435>LATD |
LD2_bit | none | BANKMASK(LATD), 2 |
LATD | none | <\077435>LATD |
LD3_bit | none | BANKMASK(LATD), 3 |
LATD | none | <\077435>LATD |
LD4_bit | none | BANKMASK(LATD), 4 |
LATD | none | <\077435>LATD |
LD5_bit | none | BANKMASK(LATD), 5 |
LATD | none | <\077435>LATD |
LD6_bit | none | BANKMASK(LATD), 6 |
LATD | none | <\077435>LATD |
LD7_bit | none | BANKMASK(LATD), 7 |
LATE | none | <\077435>LATE |
LE0_bit | none | BANKMASK(LATE), 0 |
LATE | none | <\077435>LATE |
LE1_bit | none | BANKMASK(LATE), 1 |
LATE | none | <\077435>LATE |
LE2_bit | none | BANKMASK(LATE), 2 |
LATE | none | <\077435>LATE |
LE3_bit | none | BANKMASK(LATE), 3 |
LATE | none | <\077435>LATE |
LE4_bit | none | BANKMASK(LATE), 4 |
LATE | none | <\077435>LATE |
LE5_bit | none | BANKMASK(LATE), 5 |
LATE | none | <\077435>LATE |
LE6_bit | none | BANKMASK(LATE), 6 |
LATE | none | <\077435>LATE |
LE7_bit | none | BANKMASK(LATE), 7 |
LATF | none | <\077435>LATF |
LF0_bit | none | BANKMASK(LATF), 0 |
LATF | none | <\077435>LATF |
LF1_bit | none | BANKMASK(LATF), 1 |
LATF | none | <\077435>LATF |
LF2_bit | none | BANKMASK(LATF), 2 |
LATF | none | <\077435>LATF |
LF3_bit | none | BANKMASK(LATF), 3 |
LATF | none | <\077435>LATF |
LF4_bit | none | BANKMASK(LATF), 4 |
LATF | none | <\077435>LATF |
LF5_bit | none | BANKMASK(LATF), 5 |
LATF | none | <\077435>LATF |
LF6_bit | none | BANKMASK(LATF), 6 |
LATF | none | <\077435>LATF |
LF7_bit | none | BANKMASK(LATF), 7 |
LATG | none | <\077435>LATG |
LG0_bit | none | BANKMASK(LATG), 0 |
LATG | none | <\077435>LATG |
LG1_bit | none | BANKMASK(LATG), 1 |
LATG | none | <\077435>LATG |
LG2_bit | none | BANKMASK(LATG), 2 |
LATG | none | <\077435>LATG |
LG3_bit | none | BANKMASK(LATG), 3 |
LATG | none | <\077435>LATG |
LG4_bit | none | BANKMASK(LATG), 4 |
LATH | none | <\077435>LATH |
LH0_bit | none | BANKMASK(LATH), 0 |
LATH | none | <\077435>LATH |
LH1_bit | none | BANKMASK(LATH), 1 |
LATH | none | <\077435>LATH |
LH2_bit | none | BANKMASK(LATH), 2 |
LATH | none | <\077435>LATH |
LH3_bit | none | BANKMASK(LATH), 3 |
LATH | none | <\077435>LATH |
LH4_bit | none | BANKMASK(LATH), 4 |
LATH | none | <\077435>LATH |
LH5_bit | none | BANKMASK(LATH), 5 |
LATH | none | <\077435>LATH |
LH6_bit | none | BANKMASK(LATH), 6 |
LATH | none | <\077435>LATH |
LH7_bit | none | BANKMASK(LATH), 7 |
LATJ | none | <\077435>LATJ |
LJ0_bit | none | BANKMASK(LATJ), 0 |
LATJ | none | <\077435>LATJ |
LJ1_bit | none | BANKMASK(LATJ), 1 |
LATJ | none | <\077435>LATJ |
LJ2_bit | none | BANKMASK(LATJ), 2 |
LATJ | none | <\077435>LATJ |
LJ3_bit | none | BANKMASK(LATJ), 3 |
LATJ | none | <\077435>LATJ |
LJ4_bit | none | BANKMASK(LATJ), 4 |
LATJ | none | <\077435>LATJ |
LJ5_bit | none | BANKMASK(LATJ), 5 |
LATJ | none | <\077435>LATJ |
LJ6_bit | none | BANKMASK(LATJ), 6 |
LATJ | none | <\077435>LATJ |
LJ7_bit | none | BANKMASK(LATJ), 7 |
LVDCON | none | <\077435>LVDCON |
LVDEN_bit | none | BANKMASK(LVDCON), 4 |
PIE2 | none | <\077435>PIE2 |
LVDIE_bit | none | BANKMASK(PIE2), 2 |
PIR2 | none | <\077435>PIR2 |
LVDIF_bit | none | BANKMASK(PIR2), 2 |
PORTA | none | <\077435>PORTA |
LVDIN_bit | none | BANKMASK(PORTA), 5 |
IPR2 | none | <\077435>IPR2 |
LVDIP_bit | none | BANKMASK(IPR2), 2 |
LVDCON | none | <\077435>LVDCON |
LVDL0_bit | none | BANKMASK(LVDCON), 0 |
LVDCON | none | <\077435>LVDCON |
LVDL1_bit | none | BANKMASK(LVDCON), 1 |
LVDCON | none | <\077435>LVDCON |
LVDL2_bit | none | BANKMASK(LVDCON), 2 |
LVDCON | none | <\077435>LVDCON |
LVDL3_bit | none | BANKMASK(LVDCON), 3 |
LVDCON | none | <\077435>LVDCON |
LVV0_bit | none | BANKMASK(LVDCON), 0 |
LVDCON | none | <\077435>LVDCON |
LVV1_bit | none | BANKMASK(LVDCON), 1 |
LVDCON | none | <\077435>LVDCON |
LVV2_bit | none | BANKMASK(LVDCON), 2 |
LVDCON | none | <\077435>LVDCON |
LVV3_bit | none | BANKMASK(LVDCON), 3 |
STATUS | none | <\077435>STATUS |
NEGATIVE_bit | none | BANKMASK(STATUS), 4 |
SSPSTAT | none | <\077435>SSPSTAT |
NOT_A_bit | none | BANKMASK(SSPSTAT), 5 |
SSPSTAT | none | <\077435>SSPSTAT |
NOT_ADDRESS_bit | none | BANKMASK(SSPSTAT), 5 |
RCON | none | <\077435>RCON |
NOT_BOR_bit | none | BANKMASK(RCON), 0 |
ADCON0 | none | <\077435>ADCON0 |
NOT_DONE_bit | none | BANKMASK(ADCON0), 1 |
RCON | none | <\077435>RCON |
NOT_IPEN_bit | none | BANKMASK(RCON), 7 |
RCON | none | <\077435>RCON |
NOT_PD_bit | none | BANKMASK(RCON), 2 |
RCON | none | <\077435>RCON |
NOT_POR_bit | none | BANKMASK(RCON), 1 |
INTCON2 | none | <\077435>INTCON2 |
NOT_RBPU_bit | none | BANKMASK(INTCON2), 7 |
RCON | none | <\077435>RCON |
NOT_RI_bit | none | BANKMASK(RCON), 4 |
T1CON | none | <\077435>T1CON |
NOT_T1SYNC_bit | none | BANKMASK(T1CON), 2 |
T3CON | none | <\077435>T3CON |
NOT_T3SYNC_bit | none | BANKMASK(T3CON), 2 |
RCON | none | <\077435>RCON |
NOT_TO_bit | none | BANKMASK(RCON), 3 |
SSPSTAT | none | <\077435>SSPSTAT |
NOT_W_bit | none | BANKMASK(SSPSTAT), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
NOT_WRITE_bit | none | BANKMASK(SSPSTAT), 2 |
PSPCON | none | <\077435>PSPCON |
OBF_bit | none | BANKMASK(PSPCON), 6 |
PORTJ | none | <\077435>PORTJ |
OE_bit | none | BANKMASK(PORTJ), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
OERR_bit | none | BANKMASK(RCSTA1), 1 |
RCSTA1 | none | <\077435>RCSTA1 |
OERR1_bit | none | BANKMASK(RCSTA1), 1 |
RCSTA2 | none | <\077435>RCSTA2 |
OERR2_bit | none | BANKMASK(RCSTA2), 1 |
PORTA | none | <\077435>PORTA |
OSC2_bit | none | BANKMASK(PORTA), 6 |
STATUS | none | <\077435>STATUS |
OV_bit | none | BANKMASK(STATUS), 3 |
STATUS | none | <\077435>STATUS |
OVERFLOW_bit | none | BANKMASK(STATUS), 3 |
PORTC | none | <\077435>PORTC |
PA1_bit | none | BANKMASK(PORTC), 2 |
PORTC | none | <\077435>PORTC |
PA2_bit | none | BANKMASK(PORTC), 1 |
PORTE | none | <\077435>PORTE |
PA2E_bit | none | BANKMASK(PORTE), 7 |
PORTH | none | <\077435>PORTH |
PB1_bit | none | BANKMASK(PORTH), 7 |
PORTE | none | <\077435>PORTE |
PB1E_bit | none | BANKMASK(PORTE), 6 |
PORTE | none | <\077435>PORTE |
PB2_bit | none | BANKMASK(PORTE), 2 |
PORTH | none | <\077435>PORTH |
PB3_bit | none | BANKMASK(PORTH), 5 |
PORTE | none | <\077435>PORTE |
PB3E_bit | none | BANKMASK(PORTE), 4 |
PORTH | none | <\077435>PORTH |
PC1_bit | none | BANKMASK(PORTH), 6 |
PORTE | none | <\077435>PORTE |
PC1E_bit | none | BANKMASK(PORTE), 5 |
PORTE | none | <\077435>PORTE |
PC2_bit | none | BANKMASK(PORTE), 1 |
PORTH | none | <\077435>PORTH |
PC3_bit | none | BANKMASK(PORTH), 4 |
PORTE | none | <\077435>PORTE |
PC3E_bit | none | BANKMASK(PORTE), 3 |
ADCON1 | none | <\077435>ADCON1 |
PCFG0_bit | none | BANKMASK(ADCON1), 0 |
ADCON1 | none | <\077435>ADCON1 |
PCFG1_bit | none | BANKMASK(ADCON1), 1 |
ADCON1 | none | <\077435>ADCON1 |
PCFG2_bit | none | BANKMASK(ADCON1), 2 |
ADCON1 | none | <\077435>ADCON1 |
PCFG3_bit | none | BANKMASK(ADCON1), 3 |
RCON | none | <\077435>RCON |
PD_bit | none | BANKMASK(RCON), 2 |
PORTE | none | <\077435>PORTE |
PD2_bit | none | BANKMASK(PORTE), 0 |
INTCON | none | <\077435>INTCON |
PEIE_bit | none | BANKMASK(INTCON), 6 |
INTCON | none | <\077435>INTCON |
PEIE_GIEL_bit | none | BANKMASK(INTCON), 6 |
SSPCON2 | none | <\077435>SSPCON2 |
PEN_bit | none | BANKMASK(SSPCON2), 2 |
PORTB | none | <\077435>PORTB |
PGC_bit | none | BANKMASK(PORTB), 6 |
PORTB | none | <\077435>PORTB |
PGD_bit | none | BANKMASK(PORTB), 7 |
PORTB | none | <\077435>PORTB |
PGM_bit | none | BANKMASK(PORTB), 5 |
RCON | none | <\077435>RCON |
POR_bit | none | BANKMASK(RCON), 1 |
T0CON | none | <\077435>T0CON |
PSA_bit | none | BANKMASK(T0CON), 3 |
PORTD | none | <\077435>PORTD |
PSP0_bit | none | BANKMASK(PORTD), 0 |
PORTD | none | <\077435>PORTD |
PSP1_bit | none | BANKMASK(PORTD), 1 |
PORTD | none | <\077435>PORTD |
PSP2_bit | none | BANKMASK(PORTD), 2 |
PORTD | none | <\077435>PORTD |
PSP3_bit | none | BANKMASK(PORTD), 3 |
PORTD | none | <\077435>PORTD |
PSP4_bit | none | BANKMASK(PORTD), 4 |
PORTD | none | <\077435>PORTD |
PSP5_bit | none | BANKMASK(PORTD), 5 |
PORTD | none | <\077435>PORTD |
PSP6_bit | none | BANKMASK(PORTD), 6 |
PORTD | none | <\077435>PORTD |
PSP7_bit | none | BANKMASK(PORTD), 7 |
PIE1 | none | <\077435>PIE1 |
PSPIE_bit | none | BANKMASK(PIE1), 7 |
PIR1 | none | <\077435>PIR1 |
PSPIF_bit | none | BANKMASK(PIR1), 7 |
IPR1 | none | <\077435>IPR1 |
PSPIP_bit | none | BANKMASK(IPR1), 7 |
PSPCON | none | <\077435>PSPCON |
PSPMODE_bit | none | BANKMASK(PSPCON), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA0_bit | none | BANKMASK(PORTA), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA1_bit | none | BANKMASK(PORTA), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA2_bit | none | BANKMASK(PORTA), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA3_bit | none | BANKMASK(PORTA), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA4_bit | none | BANKMASK(PORTA), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA5_bit | none | BANKMASK(PORTA), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTA | none | <\077435>PORTA |
RA6_bit | none | BANKMASK(PORTA), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB0_bit | none | BANKMASK(PORTB), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB1_bit | none | BANKMASK(PORTB), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB2_bit | none | BANKMASK(PORTB), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB3_bit | none | BANKMASK(PORTB), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB4_bit | none | BANKMASK(PORTB), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB5_bit | none | BANKMASK(PORTB), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB6_bit | none | BANKMASK(PORTB), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTB | none | <\077435>PORTB |
RB7_bit | none | BANKMASK(PORTB), 7 |
INTCON | none | <\077435>INTCON |
RBIE_bit | none | BANKMASK(INTCON), 3 |
INTCON | none | <\077435>INTCON |
RBIF_bit | none | BANKMASK(INTCON), 0 |
INTCON2 | none | <\077435>INTCON2 |
RBIP_bit | none | BANKMASK(INTCON2), 0 |
INTCON2 | none | <\077435>INTCON2 |
RBPU_bit | none | BANKMASK(INTCON2), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC0_bit | none | BANKMASK(PORTC), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC1_bit | none | BANKMASK(PORTC), 1 |
PIE1 | none | <\077435>PIE1 |
RC1IE_bit | none | BANKMASK(PIE1), 5 |
PIR1 | none | <\077435>PIR1 |
RC1IF_bit | none | BANKMASK(PIR1), 5 |
IPR1 | none | <\077435>IPR1 |
RC1IP_bit | none | BANKMASK(IPR1), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC2_bit | none | BANKMASK(PORTC), 2 |
PIE3 | none | <\077435>PIE3 |
RC2IE_bit | none | BANKMASK(PIE3), 5 |
PIR3 | none | <\077435>PIR3 |
RC2IF_bit | none | BANKMASK(PIR3), 5 |
IPR3 | none | <\077435>IPR3 |
RC2IP_bit | none | BANKMASK(IPR3), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC3_bit | none | BANKMASK(PORTC), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC4_bit | none | BANKMASK(PORTC), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC5_bit | none | BANKMASK(PORTC), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC6_bit | none | BANKMASK(PORTC), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTC | none | <\077435>PORTC |
RC7_bit | none | BANKMASK(PORTC), 7 |
RCSTA2 | none | <\077435>RCSTA2 |
RC8_92_bit | none | BANKMASK(RCSTA2), 6 |
RCSTA2 | none | <\077435>RCSTA2 |
RC92_bit | none | BANKMASK(RCSTA2), 6 |
RCSTA2 | none | <\077435>RCSTA2 |
RCD82_bit | none | BANKMASK(RCSTA2), 0 |
SSPCON2 | none | <\077435>SSPCON2 |
RCEN_bit | none | BANKMASK(SSPCON2), 3 |
PIE1 | none | <\077435>PIE1 |
RCIE_bit | none | BANKMASK(PIE1), 5 |
PIR1 | none | <\077435>PIR1 |
RCIF_bit | none | BANKMASK(PIR1), 5 |
IPR1 | none | <\077435>IPR1 |
RCIP_bit | none | BANKMASK(IPR1), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
EECON1 | none | <\077435>EECON1 |
RD_bit | none | BANKMASK(EECON1), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD0_bit | none | BANKMASK(PORTD), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD1_bit | none | BANKMASK(PORTD), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
T1CON | none | <\077435>T1CON |
RD16_bit | none | BANKMASK(T1CON), 7 |
T3CON | none | <\077435>T3CON |
RD163_bit | none | BANKMASK(T3CON), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD2_bit | none | BANKMASK(PORTD), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD3_bit | none | BANKMASK(PORTD), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD4_bit | none | BANKMASK(PORTD), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD5_bit | none | BANKMASK(PORTD), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD6_bit | none | BANKMASK(PORTD), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTD | none | <\077435>PORTD |
RD7_bit | none | BANKMASK(PORTD), 7 |
PORTE | none | <\077435>PORTE |
RDE_bit | none | BANKMASK(PORTE), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE0_bit | none | BANKMASK(PORTE), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE1_bit | none | BANKMASK(PORTE), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE2_bit | none | BANKMASK(PORTE), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE3_bit | none | BANKMASK(PORTE), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE4_bit | none | BANKMASK(PORTE), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE5_bit | none | BANKMASK(PORTE), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE6_bit | none | BANKMASK(PORTE), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTE | none | <\077435>PORTE |
RE7_bit | none | BANKMASK(PORTE), 7 |
SSPSTAT | none | <\077435>SSPSTAT |
READ_WRITE_bit | none | BANKMASK(SSPSTAT), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF0_bit | none | BANKMASK(PORTF), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF1_bit | none | BANKMASK(PORTF), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF2_bit | none | BANKMASK(PORTF), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF3_bit | none | BANKMASK(PORTF), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF4_bit | none | BANKMASK(PORTF), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF5_bit | none | BANKMASK(PORTF), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF6_bit | none | BANKMASK(PORTF), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTF | none | <\077435>PORTF |
RF7_bit | none | BANKMASK(PORTF), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTG | none | <\077435>PORTG |
RG0_bit | none | BANKMASK(PORTG), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTG | none | <\077435>PORTG |
RG1_bit | none | BANKMASK(PORTG), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTG | none | <\077435>PORTG |
RG2_bit | none | BANKMASK(PORTG), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTG | none | <\077435>PORTG |
RG3_bit | none | BANKMASK(PORTG), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTG | none | <\077435>PORTG |
RG4_bit | none | BANKMASK(PORTG), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH0_bit | none | BANKMASK(PORTH), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH1_bit | none | BANKMASK(PORTH), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH2_bit | none | BANKMASK(PORTH), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH3_bit | none | BANKMASK(PORTH), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH4_bit | none | BANKMASK(PORTH), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH5_bit | none | BANKMASK(PORTH), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH6_bit | none | BANKMASK(PORTH), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTH | none | <\077435>PORTH |
RH7_bit | none | BANKMASK(PORTH), 7 |
RCON | none | <\077435>RCON |
RI_bit | none | BANKMASK(RCON), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ0_bit | none | BANKMASK(PORTJ), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ1_bit | none | BANKMASK(PORTJ), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ2_bit | none | BANKMASK(PORTJ), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ3_bit | none | BANKMASK(PORTJ), 3 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ4_bit | none | BANKMASK(PORTJ), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ5_bit | none | BANKMASK(PORTJ), 5 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ6_bit | none | BANKMASK(PORTJ), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
PORTJ | none | <\077435>PORTJ |
RJ7_bit | none | BANKMASK(PORTJ), 7 |
SSPCON2 | none | <\077435>SSPCON2 |
RSEN_bit | none | BANKMASK(SSPCON2), 1 |
SSPSTAT | none | <\077435>SSPSTAT |
RW_bit | none | BANKMASK(SSPSTAT), 2 |
PORTC | none | <\077435>PORTC |
RX_bit | none | BANKMASK(PORTC), 7 |
PORTG | none | <\077435>PORTG |
RX2_bit | none | BANKMASK(PORTG), 2 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
RX9_bit | none | BANKMASK(RCSTA1), 6 |
RCSTA1 | none | <\077435>RCSTA1 |
RX91_bit | none | BANKMASK(RCSTA1), 6 |
RCSTA2 | none | <\077435>RCSTA2 |
RX92_bit | none | BANKMASK(RCSTA2), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
RX9D_bit | none | BANKMASK(RCSTA1), 0 |
RCSTA1 | none | <\077435>RCSTA1 |
RX9D1_bit | none | BANKMASK(RCSTA1), 0 |
RCSTA2 | none | <\077435>RCSTA2 |
RX9D2_bit | none | BANKMASK(RCSTA2), 0 |
PIE3 | none | <\077435>PIE3 |
RXB0IE_bit | none | BANKMASK(PIE3), 0 |
PIE3 | none | <\077435>PIE3 |
RXB1IE_bit | none | BANKMASK(PIE3), 1 |
PIE3 | none | <\077435>PIE3 |
RXBNIE_bit | none | BANKMASK(PIE3), 1 |
PIR3 | none | <\077435>PIR3 |
RXBNIF_bit | none | BANKMASK(PIR3), 1 |
IPR3 | none | <\077435>IPR3 |
RXBNIP_bit | none | BANKMASK(IPR3), 1 |
SSPSTAT | none | <\077435>SSPSTAT |
R_NOT_W_bit | none | BANKMASK(SSPSTAT), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
R_W_bit | none | BANKMASK(SSPSTAT), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
R_nW_bit | none | BANKMASK(SSPSTAT), 2 |
PORTC | none | <\077435>PORTC |
SCK_bit | none | BANKMASK(PORTC), 3 |
PORTC | none | <\077435>PORTC |
SCL_bit | none | BANKMASK(PORTC), 3 |
OSCCON | none | <\077435>OSCCON |
SCS_bit | none | BANKMASK(OSCCON), 0 |
PORTC | none | <\077435>PORTC |
SDA_bit | none | BANKMASK(PORTC), 4 |
PORTC | none | <\077435>PORTC |
SDI_bit | none | BANKMASK(PORTC), 4 |
PORTC | none | <\077435>PORTC |
SDO_bit | none | BANKMASK(PORTC), 5 |
SSPCON2 | none | <\077435>SSPCON2 |
SEN_bit | none | BANKMASK(SSPCON2), 0 |
TXSTA1 | none | <\077435>TXSTA1 |
SENDB_bit | none | BANKMASK(TXSTA1), 3 |
TXSTA1 | none | <\077435>TXSTA1 |
SENDB1_bit | none | BANKMASK(TXSTA1), 3 |
TXSTA2 | none | <\077435>TXSTA2 |
SENDB2_bit | none | BANKMASK(TXSTA2), 3 |
SSPSTAT | none | <\077435>SSPSTAT |
SMP_bit | none | BANKMASK(SSPSTAT), 7 |
T1CON | none | <\077435>T1CON |
SOSCEN_bit | none | BANKMASK(T1CON), 3 |
T3CON | none | <\077435>T3CON |
SOSCEN3_bit | none | BANKMASK(T3CON), 3 |
STKPTR | none | <\077435>STKPTR |
SP0_bit | none | BANKMASK(STKPTR), 0 |
STKPTR | none | <\077435>STKPTR |
SP1_bit | none | BANKMASK(STKPTR), 1 |
STKPTR | none | <\077435>STKPTR |
SP2_bit | none | BANKMASK(STKPTR), 2 |
STKPTR | none | <\077435>STKPTR |
SP3_bit | none | BANKMASK(STKPTR), 3 |
STKPTR | none | <\077435>STKPTR |
SP4_bit | none | BANKMASK(STKPTR), 4 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
SPEN_bit | none | BANKMASK(RCSTA1), 7 |
RCSTA1 | none | <\077435>RCSTA1 |
SPEN1_bit | none | BANKMASK(RCSTA1), 7 |
RCSTA2 | none | <\077435>RCSTA2 |
SPEN2_bit | none | BANKMASK(RCSTA2), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
RCSTA1 | none | <\077435>RCSTA1 |
SREN_bit | none | BANKMASK(RCSTA1), 5 |
RCSTA1 | none | <\077435>RCSTA1 |
SREN1_bit | none | BANKMASK(RCSTA1), 5 |
RCSTA2 | none | <\077435>RCSTA2 |
SREN2_bit | none | BANKMASK(RCSTA2), 5 |
RCSTA1 | none | <\077435>RCSTA1 |
SRENA_bit | none | BANKMASK(RCSTA1), 5 |
PORTF | none | <\077435>PORTF |
SS_bit | none | BANKMASK(PORTF), 7 |
PORTD | none | <\077435>PORTD |
SS2_bit | none | BANKMASK(PORTD), 7 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPEN_bit | none | BANKMASK(SSPCON1), 5 |
PIE1 | none | <\077435>PIE1 |
SSPIE_bit | none | BANKMASK(PIE1), 3 |
PIR1 | none | <\077435>PIR1 |
SSPIF_bit | none | BANKMASK(PIR1), 3 |
IPR1 | none | <\077435>IPR1 |
SSPIP_bit | none | BANKMASK(IPR1), 3 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPM0_bit | none | BANKMASK(SSPCON1), 0 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPM1_bit | none | BANKMASK(SSPCON1), 1 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPM2_bit | none | BANKMASK(SSPCON1), 2 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPM3_bit | none | BANKMASK(SSPCON1), 3 |
SSPCON1 | none | <\077435>SSPCON1 |
SSPOV_bit | none | BANKMASK(SSPCON1), 6 |
SSPSTAT | none | <\077435>SSPSTAT |
START_bit | none | BANKMASK(SSPSTAT), 3 |
STKPTR | none | <\077435>STKPTR |
STKFUL_bit | none | BANKMASK(STKPTR), 7 |
STKPTR | none | <\077435>STKPTR |
STKOVF_bit | none | BANKMASK(STKPTR), 7 |
STKPTR | none | <\077435>STKPTR |
STKPTR0_bit | none | BANKMASK(STKPTR), 0 |
STKPTR | none | <\077435>STKPTR |
STKPTR1_bit | none | BANKMASK(STKPTR), 1 |
STKPTR | none | <\077435>STKPTR |
STKPTR2_bit | none | BANKMASK(STKPTR), 2 |
STKPTR | none | <\077435>STKPTR |
STKPTR3_bit | none | BANKMASK(STKPTR), 3 |
STKPTR | none | <\077435>STKPTR |
STKPTR4_bit | none | BANKMASK(STKPTR), 4 |
STKPTR | none | <\077435>STKPTR |
STKUNF_bit | none | BANKMASK(STKPTR), 6 |
SSPSTAT | none | <\077435>SSPSTAT |
STOP_bit | none | BANKMASK(SSPSTAT), 4 |
WDTCON | none | <\077435>WDTCON |
SWDTE_bit | none | BANKMASK(WDTCON), 0 |
WDTCON | none | <\077435>WDTCON |
SWDTEN_bit | none | BANKMASK(WDTCON), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
SYNC_bit | none | BANKMASK(TXSTA1), 4 |
TXSTA1 | none | <\077435>TXSTA1 |
SYNC1_bit | none | BANKMASK(TXSTA1), 4 |
TXSTA2 | none | <\077435>TXSTA2 |
SYNC2_bit | none | BANKMASK(TXSTA2), 4 |
T0CON | none | <\077435>T0CON |
T08BIT_bit | none | BANKMASK(T0CON), 6 |
PORTA | none | <\077435>PORTA |
T0CKI_bit | none | BANKMASK(PORTA), 4 |
T0CON | none | <\077435>T0CON |
T0CS_bit | none | BANKMASK(T0CON), 5 |
INTCON | none | <\077435>INTCON |
T0IE_bit | none | BANKMASK(INTCON), 5 |
INTCON | none | <\077435>INTCON |
T0IF_bit | none | BANKMASK(INTCON), 2 |
INTCON2 | none | <\077435>INTCON2 |
T0IP_bit | none | BANKMASK(INTCON2), 2 |
T0CON | none | <\077435>T0CON |
T0PS0_bit | none | BANKMASK(T0CON), 0 |
T0CON | none | <\077435>T0CON |
T0PS1_bit | none | BANKMASK(T0CON), 1 |
T0CON | none | <\077435>T0CON |
T0PS2_bit | none | BANKMASK(T0CON), 2 |
T0CON | none | <\077435>T0CON |
T0SE_bit | none | BANKMASK(T0CON), 4 |
PORTC | none | <\077435>PORTC |
T13CKI_bit | none | BANKMASK(PORTC), 0 |
T1CON | none | <\077435>T1CON |
T1CKPS0_bit | none | BANKMASK(T1CON), 4 |
T1CON | none | <\077435>T1CON |
T1CKPS1_bit | none | BANKMASK(T1CON), 5 |
T1CON | none | <\077435>T1CON |
T1INSYNC_bit | none | BANKMASK(T1CON), 2 |
T1CON | none | <\077435>T1CON |
T1OSCEN_bit | none | BANKMASK(T1CON), 3 |
PORTC | none | <\077435>PORTC |
T1OSI_bit | none | BANKMASK(PORTC), 1 |
PORTC | none | <\077435>PORTC |
T1OSO_bit | none | BANKMASK(PORTC), 0 |
T1CON | none | <\077435>T1CON |
T1RD16_bit | none | BANKMASK(T1CON), 7 |
T1CON | none | <\077435>T1CON |
T1SYNC_bit | none | BANKMASK(T1CON), 2 |
T2CON | none | <\077435>T2CON |
T2CKPS0_bit | none | BANKMASK(T2CON), 0 |
T2CON | none | <\077435>T2CON |
T2CKPS1_bit | none | BANKMASK(T2CON), 1 |
T2CON | none | <\077435>T2CON |
T2OUTPS0_bit | none | BANKMASK(T2CON), 3 |
T2CON | none | <\077435>T2CON |
T2OUTPS1_bit | none | BANKMASK(T2CON), 4 |
T2CON | none | <\077435>T2CON |
T2OUTPS2_bit | none | BANKMASK(T2CON), 5 |
T2CON | none | <\077435>T2CON |
T2OUTPS3_bit | none | BANKMASK(T2CON), 6 |
T3CON | none | <\077435>T3CON |
T3CCP1_bit | none | BANKMASK(T3CON), 3 |
T3CON | none | <\077435>T3CON |
T3CCP2_bit | none | BANKMASK(T3CON), 6 |
T3CON | none | <\077435>T3CON |
T3CKPS0_bit | none | BANKMASK(T3CON), 4 |
T3CON | none | <\077435>T3CON |
T3CKPS1_bit | none | BANKMASK(T3CON), 5 |
T3CON | none | <\077435>T3CON |
T3INSYNC_bit | none | BANKMASK(T3CON), 2 |
T3CON | none | <\077435>T3CON |
T3NSYNC_bit | none | BANKMASK(T3CON), 2 |
T3CON | none | <\077435>T3CON |
T3RD16_bit | none | BANKMASK(T3CON), 7 |
T3CON | none | <\077435>T3CON |
T3SYNC_bit | none | BANKMASK(T3CON), 2 |
T4CON | none | <\077435>T4CON |
T4CKPS0_bit | none | BANKMASK(T4CON), 0 |
T4CON | none | <\077435>T4CON |
T4CKPS1_bit | none | BANKMASK(T4CON), 1 |
T4CON | none | <\077435>T4CON |
T4OUTPS0_bit | none | BANKMASK(T4CON), 3 |
T4CON | none | <\077435>T4CON |
T4OUTPS1_bit | none | BANKMASK(T4CON), 4 |
T4CON | none | <\077435>T4CON |
T4OUTPS2_bit | none | BANKMASK(T4CON), 5 |
T4CON | none | <\077435>T4CON |
T4OUTPS3_bit | none | BANKMASK(T4CON), 6 |
INTCON | none | <\077435>INTCON |
TMR0IE_bit | none | BANKMASK(INTCON), 5 |
INTCON | none | <\077435>INTCON |
TMR0IF_bit | none | BANKMASK(INTCON), 2 |
INTCON2 | none | <\077435>INTCON2 |
TMR0IP_bit | none | BANKMASK(INTCON2), 2 |
T0CON | none | <\077435>T0CON |
TMR0ON_bit | none | BANKMASK(T0CON), 7 |
T1CON | none | <\077435>T1CON |
TMR1CS_bit | none | BANKMASK(T1CON), 1 |
PIE1 | none | <\077435>PIE1 |
TMR1IE_bit | none | BANKMASK(PIE1), 0 |
PIR1 | none | <\077435>PIR1 |
TMR1IF_bit | none | BANKMASK(PIR1), 0 |
IPR1 | none | <\077435>IPR1 |
TMR1IP_bit | none | BANKMASK(IPR1), 0 |
T1CON | none | <\077435>T1CON |
TMR1ON_bit | none | BANKMASK(T1CON), 0 |
PIE1 | none | <\077435>PIE1 |
TMR2IE_bit | none | BANKMASK(PIE1), 1 |
PIR1 | none | <\077435>PIR1 |
TMR2IF_bit | none | BANKMASK(PIR1), 1 |
IPR1 | none | <\077435>IPR1 |
TMR2IP_bit | none | BANKMASK(IPR1), 1 |
T2CON | none | <\077435>T2CON |
TMR2ON_bit | none | BANKMASK(T2CON), 2 |
T3CON | none | <\077435>T3CON |
TMR3CS_bit | none | BANKMASK(T3CON), 1 |
PIE2 | none | <\077435>PIE2 |
TMR3IE_bit | none | BANKMASK(PIE2), 1 |
PIR2 | none | <\077435>PIR2 |
TMR3IF_bit | none | BANKMASK(PIR2), 1 |
IPR2 | none | <\077435>IPR2 |
TMR3IP_bit | none | BANKMASK(IPR2), 1 |
T3CON | none | <\077435>T3CON |
TMR3ON_bit | none | BANKMASK(T3CON), 0 |
PIE3 | none | <\077435>PIE3 |
TMR4IE_bit | none | BANKMASK(PIE3), 3 |
PIR3 | none | <\077435>PIR3 |
TMR4IF_bit | none | BANKMASK(PIR3), 3 |
IPR3 | none | <\077435>IPR3 |
TMR4IP_bit | none | BANKMASK(IPR3), 3 |
T4CON | none | <\077435>T4CON |
TMR4ON_bit | none | BANKMASK(T4CON), 2 |
RCON | none | <\077435>RCON |
TO_bit | none | BANKMASK(RCON), 3 |
TRISA | none | <\077435>TRISA |
TRISA0_bit | none | BANKMASK(TRISA), 0 |
TRISA | none | <\077435>TRISA |
TRISA1_bit | none | BANKMASK(TRISA), 1 |
TRISA | none | <\077435>TRISA |
TRISA2_bit | none | BANKMASK(TRISA), 2 |
TRISA | none | <\077435>TRISA |
TRISA3_bit | none | BANKMASK(TRISA), 3 |
TRISA | none | <\077435>TRISA |
TRISA4_bit | none | BANKMASK(TRISA), 4 |
TRISA | none | <\077435>TRISA |
TRISA5_bit | none | BANKMASK(TRISA), 5 |
TRISA | none | <\077435>TRISA |
TRISA6_bit | none | BANKMASK(TRISA), 6 |
TRISB | none | <\077435>TRISB |
TRISB0_bit | none | BANKMASK(TRISB), 0 |
TRISB | none | <\077435>TRISB |
TRISB1_bit | none | BANKMASK(TRISB), 1 |
TRISB | none | <\077435>TRISB |
TRISB2_bit | none | BANKMASK(TRISB), 2 |
TRISB | none | <\077435>TRISB |
TRISB3_bit | none | BANKMASK(TRISB), 3 |
TRISB | none | <\077435>TRISB |
TRISB4_bit | none | BANKMASK(TRISB), 4 |
TRISB | none | <\077435>TRISB |
TRISB5_bit | none | BANKMASK(TRISB), 5 |
TRISB | none | <\077435>TRISB |
TRISB6_bit | none | BANKMASK(TRISB), 6 |
TRISB | none | <\077435>TRISB |
TRISB7_bit | none | BANKMASK(TRISB), 7 |
TRISC | none | <\077435>TRISC |
TRISC0_bit | none | BANKMASK(TRISC), 0 |
TRISC | none | <\077435>TRISC |
TRISC1_bit | none | BANKMASK(TRISC), 1 |
TRISC | none | <\077435>TRISC |
TRISC2_bit | none | BANKMASK(TRISC), 2 |
TRISC | none | <\077435>TRISC |
TRISC3_bit | none | BANKMASK(TRISC), 3 |
TRISC | none | <\077435>TRISC |
TRISC4_bit | none | BANKMASK(TRISC), 4 |
TRISC | none | <\077435>TRISC |
TRISC5_bit | none | BANKMASK(TRISC), 5 |
TRISC | none | <\077435>TRISC |
TRISC6_bit | none | BANKMASK(TRISC), 6 |
TRISC | none | <\077435>TRISC |
TRISC7_bit | none | BANKMASK(TRISC), 7 |
TRISD | none | <\077435>TRISD |
TRISD0_bit | none | BANKMASK(TRISD), 0 |
TRISD | none | <\077435>TRISD |
TRISD1_bit | none | BANKMASK(TRISD), 1 |
TRISD | none | <\077435>TRISD |
TRISD2_bit | none | BANKMASK(TRISD), 2 |
TRISD | none | <\077435>TRISD |
TRISD3_bit | none | BANKMASK(TRISD), 3 |
TRISD | none | <\077435>TRISD |
TRISD4_bit | none | BANKMASK(TRISD), 4 |
TRISD | none | <\077435>TRISD |
TRISD5_bit | none | BANKMASK(TRISD), 5 |
TRISD | none | <\077435>TRISD |
TRISD6_bit | none | BANKMASK(TRISD), 6 |
TRISD | none | <\077435>TRISD |
TRISD7_bit | none | BANKMASK(TRISD), 7 |
TRISE | none | <\077435>TRISE |
TRISE0_bit | none | BANKMASK(TRISE), 0 |
TRISE | none | <\077435>TRISE |
TRISE1_bit | none | BANKMASK(TRISE), 1 |
TRISE | none | <\077435>TRISE |
TRISE2_bit | none | BANKMASK(TRISE), 2 |
TRISE | none | <\077435>TRISE |
TRISE3_bit | none | BANKMASK(TRISE), 3 |
TRISE | none | <\077435>TRISE |
TRISE4_bit | none | BANKMASK(TRISE), 4 |
TRISE | none | <\077435>TRISE |
TRISE5_bit | none | BANKMASK(TRISE), 5 |
TRISE | none | <\077435>TRISE |
TRISE6_bit | none | BANKMASK(TRISE), 6 |
TRISE | none | <\077435>TRISE |
TRISE7_bit | none | BANKMASK(TRISE), 7 |
TRISF | none | <\077435>TRISF |
TRISF0_bit | none | BANKMASK(TRISF), 0 |
TRISF | none | <\077435>TRISF |
TRISF1_bit | none | BANKMASK(TRISF), 1 |
TRISF | none | <\077435>TRISF |
TRISF2_bit | none | BANKMASK(TRISF), 2 |
TRISF | none | <\077435>TRISF |
TRISF3_bit | none | BANKMASK(TRISF), 3 |
TRISF | none | <\077435>TRISF |
TRISF4_bit | none | BANKMASK(TRISF), 4 |
TRISF | none | <\077435>TRISF |
TRISF5_bit | none | BANKMASK(TRISF), 5 |
TRISF | none | <\077435>TRISF |
TRISF6_bit | none | BANKMASK(TRISF), 6 |
TRISF | none | <\077435>TRISF |
TRISF7_bit | none | BANKMASK(TRISF), 7 |
TRISG | none | <\077435>TRISG |
TRISG0_bit | none | BANKMASK(TRISG), 0 |
TRISG | none | <\077435>TRISG |
TRISG1_bit | none | BANKMASK(TRISG), 1 |
TRISG | none | <\077435>TRISG |
TRISG2_bit | none | BANKMASK(TRISG), 2 |
TRISG | none | <\077435>TRISG |
TRISG3_bit | none | BANKMASK(TRISG), 3 |
TRISG | none | <\077435>TRISG |
TRISG4_bit | none | BANKMASK(TRISG), 4 |
TRISH | none | <\077435>TRISH |
TRISH0_bit | none | BANKMASK(TRISH), 0 |
TRISH | none | <\077435>TRISH |
TRISH1_bit | none | BANKMASK(TRISH), 1 |
TRISH | none | <\077435>TRISH |
TRISH2_bit | none | BANKMASK(TRISH), 2 |
TRISH | none | <\077435>TRISH |
TRISH3_bit | none | BANKMASK(TRISH), 3 |
TRISH | none | <\077435>TRISH |
TRISH4_bit | none | BANKMASK(TRISH), 4 |
TRISH | none | <\077435>TRISH |
TRISH5_bit | none | BANKMASK(TRISH), 5 |
TRISH | none | <\077435>TRISH |
TRISH6_bit | none | BANKMASK(TRISH), 6 |
TRISH | none | <\077435>TRISH |
TRISH7_bit | none | BANKMASK(TRISH), 7 |
TRISJ | none | <\077435>TRISJ |
TRISJ0_bit | none | BANKMASK(TRISJ), 0 |
TRISJ | none | <\077435>TRISJ |
TRISJ1_bit | none | BANKMASK(TRISJ), 1 |
TRISJ | none | <\077435>TRISJ |
TRISJ2_bit | none | BANKMASK(TRISJ), 2 |
TRISJ | none | <\077435>TRISJ |
TRISJ3_bit | none | BANKMASK(TRISJ), 3 |
TRISJ | none | <\077435>TRISJ |
TRISJ4_bit | none | BANKMASK(TRISJ), 4 |
TRISJ | none | <\077435>TRISJ |
TRISJ5_bit | none | BANKMASK(TRISJ), 5 |
TRISJ | none | <\077435>TRISJ |
TRISJ6_bit | none | BANKMASK(TRISJ), 6 |
TRISJ | none | <\077435>TRISJ |
TRISJ7_bit | none | BANKMASK(TRISJ), 7 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
TRMT_bit | none | BANKMASK(TXSTA1), 1 |
TXSTA1 | none | <\077435>TXSTA1 |
TRMT1_bit | none | BANKMASK(TXSTA1), 1 |
TXSTA2 | none | <\077435>TXSTA2 |
TRMT2_bit | none | BANKMASK(TXSTA2), 1 |
PORTC | none | <\077435>PORTC |
TX_bit | none | BANKMASK(PORTC), 6 |
PIE1 | none | <\077435>PIE1 |
TX1IE_bit | none | BANKMASK(PIE1), 4 |
PIR1 | none | <\077435>PIR1 |
TX1IF_bit | none | BANKMASK(PIR1), 4 |
IPR1 | none | <\077435>IPR1 |
TX1IP_bit | none | BANKMASK(IPR1), 4 |
PORTG | none | <\077435>PORTG |
TX2_bit | none | BANKMASK(PORTG), 1 |
PIE3 | none | <\077435>PIE3 |
TX2IE_bit | none | BANKMASK(PIE3), 4 |
PIR3 | none | <\077435>PIR3 |
TX2IF_bit | none | BANKMASK(PIR3), 4 |
IPR3 | none | <\077435>IPR3 |
TX2IP_bit | none | BANKMASK(IPR3), 4 |
TXSTA2 | none | <\077435>TXSTA2 |
TX8_92_bit | none | BANKMASK(TXSTA2), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
TX9_bit | none | BANKMASK(TXSTA1), 6 |
TXSTA1 | none | <\077435>TXSTA1 |
TX91_bit | none | BANKMASK(TXSTA1), 6 |
TXSTA2 | none | <\077435>TXSTA2 |
TX92_bit | none | BANKMASK(TXSTA2), 6 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
TX9D_bit | none | BANKMASK(TXSTA1), 0 |
TXSTA1 | none | <\077435>TXSTA1 |
TX9D1_bit | none | BANKMASK(TXSTA1), 0 |
TXSTA2 | none | <\077435>TXSTA2 |
TX9D2_bit | none | BANKMASK(TXSTA2), 0 |
PIE3 | none | <\077435>PIE3 |
TXB0IE_bit | none | BANKMASK(PIE3), 2 |
PIE3 | none | <\077435>PIE3 |
TXB1IE_bit | none | BANKMASK(PIE3), 3 |
PIE3 | none | <\077435>PIE3 |
TXB2IE_bit | none | BANKMASK(PIE3), 4 |
PIE3 | none | <\077435>PIE3 |
TXBNIE_bit | none | BANKMASK(PIE3), 4 |
PIR3 | none | <\077435>PIR3 |
TXBNIF_bit | none | BANKMASK(PIR3), 4 |
IPR3 | none | <\077435>IPR3 |
TXBNIP_bit | none | BANKMASK(IPR3), 4 |
TXSTA2 | none | <\077435>TXSTA2 |
TXD82_bit | none | BANKMASK(TXSTA2), 0 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
TXSTA1 | none | <\077435>TXSTA1 |
TXEN_bit | none | BANKMASK(TXSTA1), 5 |
TXSTA1 | none | <\077435>TXSTA1 |
TXEN1_bit | none | BANKMASK(TXSTA1), 5 |
TXSTA2 | none | <\077435>TXSTA2 |
TXEN2_bit | none | BANKMASK(TXSTA2), 5 |
PIE1 | none | <\077435>PIE1 |
TXIE_bit | none | BANKMASK(PIE1), 4 |
PIR1 | none | <\077435>PIR1 |
TXIF_bit | none | BANKMASK(PIR1), 4 |
IPR1 | none | <\077435>IPR1 |
TXIP_bit | none | BANKMASK(IPR1), 4 |
SSPSTAT | none | <\077435>SSPSTAT |
UA_bit | none | BANKMASK(SSPSTAT), 1 |
PORTJ | none | <\077435>PORTJ |
UB_bit | none | BANKMASK(PORTJ), 7 |
PORTA | none | <\077435>PORTA |
ULPWUIN_bit | none | BANKMASK(PORTA), 0 |
ADCON1 | none | <\077435>ADCON1 |
VCFG0_bit | none | BANKMASK(ADCON1), 4 |
ADCON1 | none | <\077435>ADCON1 |
VCFG01_bit | none | BANKMASK(ADCON1), 4 |
ADCON1 | none | <\077435>ADCON1 |
VCFG1_bit | none | BANKMASK(ADCON1), 5 |
ADCON1 | none | <\077435>ADCON1 |
VCFG11_bit | none | BANKMASK(ADCON1), 5 |
PORTA | none | <\077435>PORTA |
VREFM_bit | none | BANKMASK(PORTA), 2 |
PORTA | none | <\077435>PORTA |
VREFP_bit | none | BANKMASK(PORTA), 3 |
MEMCON | none | <\077435>MEMCON |
WAIT0_bit | none | BANKMASK(MEMCON), 4 |
MEMCON | none | <\077435>MEMCON |
WAIT1_bit | none | BANKMASK(MEMCON), 5 |
SSPCON1 | none | <\077435>SSPCON1 |
WCOL_bit | none | BANKMASK(SSPCON1), 7 |
MEMCON | none | <\077435>MEMCON |
WM0_bit | none | BANKMASK(MEMCON), 0 |
MEMCON | none | <\077435>MEMCON |
WM1_bit | none | BANKMASK(MEMCON), 1 |
_DEPRECATED | none | __attribute__((__deprecated__)) |
EECON1 | none | <\077435>EECON1 |
WR_bit | none | BANKMASK(EECON1), 1 |
PORTE | none | <\077435>PORTE |
WRE_bit | none | BANKMASK(PORTE), 1 |
EECON1 | none | <\077435>EECON1 |
WREN_bit | none | BANKMASK(EECON1), 2 |
EECON1 | none | <\077435>EECON1 |
WRERR_bit | none | BANKMASK(EECON1), 3 |
PORTJ | none | <\077435>PORTJ |
WRH_bit | none | BANKMASK(PORTJ), 3 |
PORTJ | none | <\077435>PORTJ |
WRL_bit | none | BANKMASK(PORTJ), 2 |
STATUS | none | <\077435>STATUS |
ZERO_bit | none | BANKMASK(STATUS), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
nA_bit | none | BANKMASK(SSPSTAT), 5 |
SSPSTAT | none | <\077435>SSPSTAT |
nADDRESS_bit | none | BANKMASK(SSPSTAT), 5 |
RCON | none | <\077435>RCON |
nBOR_bit | none | BANKMASK(RCON), 0 |
ADCON0 | none | <\077435>ADCON0 |
nDONE_bit | none | BANKMASK(ADCON0), 1 |
RCON | none | <\077435>RCON |
nIPEN_bit | none | BANKMASK(RCON), 7 |
RCON | none | <\077435>RCON |
nPD_bit | none | BANKMASK(RCON), 2 |
RCON | none | <\077435>RCON |
nPOR_bit | none | BANKMASK(RCON), 1 |
INTCON2 | none | <\077435>INTCON2 |
nRBPU_bit | none | BANKMASK(INTCON2), 7 |
RCON | none | <\077435>RCON |
nRI_bit | none | BANKMASK(RCON), 4 |
T1CON | none | <\077435>T1CON |
nT1SYNC_bit | none | BANKMASK(T1CON), 2 |
T3CON | none | <\077435>T3CON |
nT3SYNC_bit | none | BANKMASK(T3CON), 2 |
RCON | none | <\077435>RCON |
nTO_bit | none | BANKMASK(RCON), 3 |
SSPSTAT | none | <\077435>SSPSTAT |
nW_bit | none | BANKMASK(SSPSTAT), 2 |
SSPSTAT | none | <\077435>SSPSTAT |
nWRITE_bit | none | BANKMASK(SSPSTAT), 2 |
_NO_PLIB_SUPPORT | 1 | __attribute__((__unsupported__("The " <0> " routine is no longer supported. Please use the MPLAB X MCC."))) |
_NO_PLIB_SUPPORT | 1 | __attribute__((__unsupported__("The " <0> " routine is no longer supported. Please use the MPLAB X MCC."))) |
_NO_PLIB_SUPPORT | 1 | __attribute__((__unsupported__("The " <0> " routine is no longer supported. Please use the MPLAB X MCC."))) |
FLASH_WRITE | 3 | flash_write(<0>,<1>,<2>) |
flash_erase | 1 | EraseFlash(<0>,(<0>)+1) |
FLASH_ERASE | 1 | EraseFlash(<0>,(<0>)+1) |
_ERRATA_H_ | none | |
ERRATA_4000 | none | (1<<0) |
ERRATA_FASTINTS | none | (1<<1) |
ERRATA_LFSR | none | (1<<2) |
ERRATA_MINUS40 | none | (1<<3) |
ERRATA_RESET | none | (1<<4) |
ERRATA_BSR15 | none | (1<<5) |
ERRATA_DAW | none | (1<<6) |
ERRATA_EEDATARD | none | (1<<7) |
ERRATA_EEADR | none | (1<<8) |
ERRATA_EE_LVD | none | (1<<9) |
ERRATA_FL_LVD | none | (1<<10) |
ERRATA_TBLWTINT | none | (1<<11) |
ERRATA_FW4000 | none | (1<<12) |
ERRATA_RESETRAM | none | (1<<13) |
ERRATA_FETCH | none | (1<<14) |
LOW_BYTE | 1 | ((unsigned char)((<0>)&0xFF)) |
HIGH_BYTE | 1 | ((unsigned char)(((<0>)>>8)&0xFF)) |
LOW_WORD | 1 | ((unsigned short)((<0>)&0xFFFF)) |
HIGH_WORD | 1 | ((unsigned short)(((<0>)>>16)&0xFFFF)) |
CLRWDT | empty | asm(" clrwdt") |
ClrWdt | empty | asm(" clrwdt") |
NOP | empty | __nop() |
Nop | empty | __nop() |
Reset | empty | asm(" reset") |
SLEEP | empty | asm(" sleep") |
Sleep | empty | asm(" sleep") |
__PROG_CONFIG | 2 | __config(___mkstr(<\077435>__PROG_CONFIG), ___mkstr(pic18), <0>, <1>) |
__CONFIG | 2 | __config(___mkstr(<\077435>__CONFIG), ___mkstr(pic18), ___mkstr(<1>)) |
__IDLOC | 1 | __config(___mkstr(<\077435>__IDLOC), ___mkstr(pic18), ___mkstr(<0>)) |
_EEPROMSIZE | none | 1024 |
__EEPROM_DATA | 8 | asm("\tpsect eeprom_data,class=EEDATA,noexec"); asm("\tdb\t" ___mkstr(<0>) "," ___mkstr(<1>) "," ___mkstr(<2>) "," ___mkstr(<3>) "," ___mkstr(<4>) "," ___mkstr(<5>) "," ___mkstr(<6>) "," ___mkstr(<7>)) |
_EEPROMSIZE | none | 1024 |
_EEPROMSIZE | none | 1024 |
_LOAD_EEADR | 1 | (EEADRH=(((<0>)>>8)&0xFF),EEADR=((<0>)&0xFF)) |
_EEPROMSIZE | none | 1024 |
_CLEAR_EEIF | empty | PIR2bits.EEIF=0 |
_LOAD_TBLPTR | 1 | *((far unsigned char**)&TBLPTR)=(far unsigned char*)(<0>) |
_NO_PLIB_SUPPORT | 1 | __attribute__((__unsupported__("The " <0> " routine is no longer supported. Please use the MPLAB X MCC."))) |
_NO_PLIB_SUPPORT | 1 | __attribute__((__unsupported__("The " <0> " routine is no longer supported. Please use the MPLAB X MCC."))) |
_NO_PLIB_SUPPORT | 1 | __attribute__((__unsupported__("The " <0> " routine is no longer supported. Please use the MPLAB X MCC."))) |
EEPROM_READ | 1 | Read_b_eep(<0>) |
eeprom_read | 1 | Read_b_eep(<0>) |
EEPROM_WRITE | 2 | (Busy_eep(), Write_b_eep(<0>,<1>)) |
eeprom_write | 2 | (Busy_eep(), Write_b_eep(<0>,<1>)) |
WRITETIMER0 | 1 | ((void)(TMR0H=((<0>)>>8),TMR0L=((<0>)&0xFF))) |
WRITETIMER1 | 1 | ((void)(TMR1H=((<0>)>>8),TMR1L=((<0>)&0xFF))) |
WRITETIMER3 | 1 | ((void)(TMR3H=((<0>)>>8),TMR3L=((<0>)&0xFF))) |
READTIMER0 | empty | (TMR0) |
READTIMER1 | empty | (TMR1) |
READTIMER3 | empty | (TMR3) |
T1RD16ON | none | __t1rd16on() |
T3RD16ON | none | __t3rd16on() |
__delay_us | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000000.0))) |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
__delaywdt_us | 1 | _delaywdt((unsigned long)((<0>)*(_XTAL_FREQ/4000000.0))) |
__delaywdt_ms | 1 | _delaywdt((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_INTCONbits | none | INTCONbits |
ei | empty | (_INTCONbits.GIE = 1) |
di | empty | (_INTCONbits.GIE = 0) |
_STDIO_H_ | none | |
___SIZE_T_H_ | none | |
NULL | none | (0) |
BUFSIZ | none | 1024 |
_NFILE | none | 20 |
va_start | 2 | *<0> = __va_start() |
va_arg | 2 | (*(<1> *)__va_arg((*(<1> **)<0>), (<1>)0)) |
_STDARG | none | |
va_end | 1 | |
_IOFBF | none | 0 |
_IOREAD | none | 01 |
_IOWRT | none | 02 |
_IORW | none | 03 |
_IONBF | none | 04 |
_IOMYBUF | none | 010 |
_IOEOF | none | 020 |
_IOERR | none | 040 |
_IOSTRG | none | 0100 |
_IOBINARY | none | 0200 |
_IOLBF | none | 0400 |
_IODIRN | none | 01000 |
_IOAPPEND | none | 02000 |
_IOSEEKED | none | 04000 |
_IOTMPFILE | none | 010000 |
EOF | none | (-1) |
_IOSTRING | none | (-67) |
SEEK_SET | none | 0 |
SEEK_CUR | none | 1 |
SEEK_END | none | 2 |
TMP_MAX | none | 255 |
_CONIO_H_ | none | |
_ERRNO_H_ | none | |
EDOM | none | 33 |
ERANGE | none | 34 |
getchar | empty | getche() |
putchar | 1 | putch(<0>) |
getc | 1 | fgetc(<0>) |
putc | 2 | fputc(<0>,<1>) |
feof | 1 | (((<0>)->_flag&_IOEOF)!=0) |
ferror | 1 | (((<0>)->_flag&_IOERR)!=0) |
fileno | 1 | ((unsigned short)<0>->_file) |
clrerr | 1 | <0>->_flag &= ~_IOERR |
clreof | 1 | <0>->_flag &= ~_IOEOF |
clearerr | 1 | <0>->_flag &= ~(_IOERR|_IOEOF) |
_STDLIB_H_ | none | |
RAND_MAX | none | 32767 |
EXIT_SUCCESS | none | 0 |
EXIT_FAILURE | none | 1 |
_DIVTYPES | none | |
strtoul | 3 | ((unsigned long)strtol((<0>),(<1>),(<2>))) |
max | 2 | (((<0>) > (<1>)) ? (<0>) : (<1>)) |
min | 2 | (((<0>) < (<1>)) ? (<0>) : (<1>)) |
__PIC18F8720A__ | none | |
XC_HEADER_TEMPLATE_H | none | |
i2c_LIB | none | |
Output | none | 0 |
Input | none | 1 |
_SW | none | 0 |
_HW | none | 1 |
SCL_CLOCK | none | 1000000L |
_XTAL_FREQ | none | 30000000 |
int8_t | none | <\077435>int8_t |
INT8_MIN | none | (-128) |
INT8_MAX | none | (127) |
int16_t | none | <\077435>int16_t |
INT16_MIN | none | (-32768) |
INT16_MAX | none | (32767) |
int24_t | none | <\077435>int24_t |
INT24_MIN | none | (-8388608L) |
INT24_MAX | none | (8388607L) |
int32_t | none | <\077435>int32_t |
INT32_MIN | none | (-2147483648L) |
INT32_MAX | none | (2147483647L) |
uint8_t | none | <\077435>uint8_t |
UINT8_MAX | none | (255) |
uint16_t | none | <\077435>uint16_t |
UINT16_MAX | none | (65535U) |
uint24_t | none | <\077435>uint24_t |
UINT24_MAX | none | (16777215UL) |
uint32_t | none | <\077435>uint32_t |
UINT32_MAX | none | (4294967295UL) |
int_least8_t | none | <\077435>int_least8_t |
INT_LEAST8_MIN | none | (-128) |
INT_LEAST8_MAX | none | (127) |
int_least16_t | none | <\077435>int_least16_t |
INT_LEAST16_MIN | none | (-32768) |
INT_LEAST16_MAX | none | (32767) |
INT_LEAST24_MIN | none | (-8388608L) |
INT_LEAST24_MAX | none | (8388607L) |
int_least24_t | none | <\077435>int_least24_t |
int_least32_t | none | <\077435>int_least32_t |
INT_LEAST32_MIN | none | (-2147483648L) |
INT_LEAST32_MAX | none | (2147483647L) |
uint_least8_t | none | <\077435>uint_least8_t |
UINT_LEAST8_MAX | none | (255) |
uint_least16_t | none | <\077435>uint_least16_t |
UINT_LEAST16_MAX | none | (65535UL) |
UINT_LEAST24_MAX | none | (16777215UL) |
uint_least24_t | none | <\077435>uint_least24_t |
uint_least32_t | none | <\077435>uint_least32_t |
UINT_LEAST32_MAX | none | (4294967295UL) |
int_fast8_t | none | <\077435>int_fast8_t |
INT_FAST8_MIN | none | (-128) |
INT_FAST8_MAX | none | (127) |
int_fast16_t | none | <\077435>int_fast16_t |
INT_FAST16_MIN | none | (-32768) |
INT_FAST16_MAX | none | (32767) |
INT_FAST24_MIN | none | (-8388608L) |
INT_FAST24_MAX | none | (8388607L) |
int_fast24_t | none | <\077435>int_fast24_t |
int_fast32_t | none | <\077435>int_fast32_t |
INT_FAST32_MIN | none | (-2147483648L) |
INT_FAST32_MAX | none | (2147483647L) |
uint_fast8_t | none | <\077435>uint_fast8_t |
UINT_FAST8_MAX | none | (255) |
uint_fast16_t | none | <\077435>uint_fast16_t |
UINT_FAST16_MAX | none | (65535UL) |
UINT_FAST24_MAX | none | (16777215UL) |
uint_fast24_t | none | <\077435>uint_fast24_t |
uint_fast32_t | none | <\077435>uint_fast32_t |
UINT_FAST32_MAX | none | (4294967295UL) |
int32_t | none | <\077435>int32_t |
intmax_t | none | <\077435>intmax_t |
uint32_t | none | <\077435>uint32_t |
uintmax_t | none | <\077435>uintmax_t |
int16_t | none | <\077435>int16_t |
intptr_t | none | <\077435>intptr_t |
uint16_t | none | <\077435>uint16_t |
uintptr_t | none | <\077435>uintptr_t |
_wt_speed_i2c_Master | none | (((_XTAL_FREQ/SCL_CLOCK)-16)/2) |
SCL_MasterSW | none | PORTBbits.RB0 |
SDA_MasterSW | none | PORTBbits.RB1 |
SCL_MasterSW_PIN | none | 0 |
SDA_MasterSW_PIN | none | 1 |
SCLt_MasterSW | none | TRISBbits.TRISB0 |
SDAt_MasterSW | none | TRISBbits.TRISB1 |
SCL_MasterHW | none | PORTCbits.RC3 |
SDA_MasterHW | none | PORTCbits.RC4 |
SCL_MasterHW_PIN | none | 3 |
SDA_MasterHW_PIN | none | 4 |
SCLt_MasterHW | none | TRISCbits.TRISC3 |
SDAt_MasterHW | none | TRISCbits.TRISC4 |
ACKNOWLEDGE | none | 1 |
NOT_ACKNOWLEDGE | none | 0 |
SSPIF | none | 3 |
BitTest | 2 | (<0> & (0x01 << <1>)) |
BitSet | 2 | (<0> |= (1<<<1>)) |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
BitNeg | 2 | (<0> ^= (1<<<1>)) |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
__PIC18F8720A__ | none | |
display_LIB | none | |
_XTAL_FREQ | none | 30000000 |
Output | none | 0 |
Input | none | 1 |
_Hour_hi_A | none | PORTDbits.RD0 |
_Hour_hi_B | none | PORTDbits.RD1 |
_Hour_hi_C | none | PORTDbits.RD2 |
_Hour_hi_D | none | PORTDbits.RD3 |
_Hour_hi_E | none | PORTDbits.RD4 |
_Hour_hi_F | none | PORTDbits.RD5 |
_Hour_hi_G | none | PORTDbits.RD6 |
_Hour_hi_DT | none | PORTDbits.RD7 |
_Hour_port_hi | none | PORTD |
tHour_hi | none | TRISD |
TTL_Hour_hiD_LAT | none | LATD |
TTL_Segment_DT_D | none | 7 |
_Hour_lo_A | none | PORTEbits.RE0 |
_Hour_lo_B | none | PORTEbits.RE1 |
_Hour_lo_C | none | PORTEbits.RE2 |
_Hour_lo_D | none | PORTEbits.RE3 |
_Hour_lo_E | none | PORTEbits.RE4 |
_Hour_lo_F | none | PORTEbits.RE5 |
_Hour_lo_G | none | PORTEbits.RE6 |
_Hour_lo_DT | none | PORTEbits.RE7 |
_Hour_port_lo | none | PORTE |
tHour_lo | none | TRISE |
TTL_Hour_loE_LAT | none | LATE |
TTL_Segment_DT_E | none | TTL_Segment_DT_D |
_Minut_hi_A | none | PORTHbits.RH0 |
_Minut_hi_B | none | PORTHbits.RH1 |
_Minut_hi_C | none | PORTHbits.RH2 |
_Minut_hi_D | none | PORTHbits.RH3 |
_Minut_hi_E | none | PORTHbits.RH4 |
_Minut_hi_F | none | PORTHbits.RH5 |
_Minut_hi_G | none | PORTHbits.RH6 |
_Minut_hi_DT | none | PORTHbits.RH7 |
_Minut_port_hi | none | PORTH |
tMinut_hi | none | TRISH |
TTL_Minut_hiH_LAT | none | LATH |
TTL_Segment_DT_H | none | TTL_Segment_DT_D |
_Minut_lo_A | none | PORTJbits.RJ0 |
_Minut_lo_B | none | PORTJbits.RJ1 |
_Minut_lo_C | none | PORTJbits.RJ2 |
_Minut_lo_D | none | PORTJbits.RJ3 |
_Minut_lo_E | none | PORTJbits.RJ4 |
_Minut_lo_F | none | PORTJbits.RJ5 |
_Minut_lo_G | none | PORTJbits.RJ6 |
_Minut_lo_DT | none | PORTJbits.RJ7 |
_Minut_port_lo | none | PORTJ |
tMinut_lo | none | TRISJ |
TTL_Minut_loJ_LAT | none | LATJ |
TTL_Segment_DT_J | none | TTL_Segment_DT_D |
_Second_hi_A | none | PORTFbits.RF0 |
_Second_hi_B | none | PORTFbits.RF1 |
_Second_hi_C | none | PORTFbits.RF2 |
_Second_hi_D | none | PORTFbits.RF3 |
_Second_hi_E | none | PORTFbits.RF4 |
_Second_hi_F | none | PORTFbits.RF5 |
_Second_hi_G | none | PORTFbits.RF6 |
_Second_hi_DT | none | PORTFbits.RF7 |
_Second_port_hi | none | PORTF |
tSecond_hi | none | TRISF |
TTL_Second_hiF_LAT | none | LATF |
TTL_Segment_DT_F | none | TTL_Segment_DT_D |
_Second_lo_A | none | PORTGbits.RG0 |
_Second_lo_B | none | PORTGbits.RG1 |
_Second_lo_C | none | PORTGbits.RG2 |
_Second_lo_D | none | PORTGbits.RG3 |
_Second_lo_E | none | PORTGbits.RG4 |
_Second_lo_F | none | 0 |
_Second_lo_G | none | 1 |
_Second_lo_DT | none | 2 |
tSecond_lo | none | TRISG |
tSecond_lo_F | none | TRISCbits.TRISC0 |
tSecond_lo_G | none | TRISCbits.TRISC1 |
tSecond_lo_DT | none | TRISCbits.TRISC2 |
_Second_port_loh | none | PORTG |
_Second_port_lol | none | PORTC |
TTL_Segment_DT_C | none | _Second_lo_DT |
_TTL_GLOW_HH | none | 0 |
_TTL_GLOW_HL | none | 1 |
_TTL_GLOW_MH | none | 2 |
_TTL_GLOW_ML | none | 3 |
_TTL_GLOW_SH | none | 4 |
_TTL_GLOW_SL | none | 5 |
tTTL_GLOW | none | TRISA |
TTL_GLOW_PORT | none | PORTA |
TTL_GLOW_LAT | none | LATA |
TTL_GLOW_ADCON1 | none | ADCON1 |
T0CS | none | 5 |
TMR0ON | none | 7 |
T0SE | none | 4 |
tTTL_HourHi | none | TRISD |
TTL_HourHi_PORT | none | PORTD |
TTL_HourHi_LAT | none | LATD |
tTTL_HourLo | none | TRISE |
TTL_HourLo_PORT | none | PORTE |
TTL_HourLo_LAT | none | LATE |
tTTL_MinitHi | none | TRISH |
TTL_MinitHi_PORT | none | PORTH |
TTL_MinitHi_LAT | none | LATH |
TTL_MinitHi_ADCON1 | none | ADCON1 |
tTTL_MinitLo | none | TRISJ |
TTL_MinitLo_PORT | none | PORTJ |
TTL_MinitLo_LAT | none | LATJ |
tTTL_SecondHi | none | TRISF |
TTL_SecondHi_PORT | none | PORTF |
TTL_SecondHi_LAT | none | LATF |
TTL_SecondHi_ADCON1 | none | ADCON1 |
TTL_SecondHi_CMCON | none | CMCON |
tTTL_SecondLoG | none | TRISG |
TTL_SecondLoG_PORT | none | PORTG |
TTL_SecondLoG_LAT | none | LATG |
TTL_Segment_SLF | none | 0 |
TTL_Segment_SLG | none | 1 |
TTL_Segment_SLT | none | 2 |
tTTL_SecondSLF | none | TRISCbits.TRISC0 |
tTTL_SecondSLG | none | TRISCbits.TRISC1 |
tTTL_SecondSLT | none | TRISCbits.TRISC2 |
tTTL_SecondLoC | none | TRISC |
TTL_SecondLoC_PORT | none | PORTC |
TTL_SecondLoC_LAT | none | LATC |
CCP1IE | none | 2 |
TMR1CS | none | 1 |
TMR1ON | none | 0 |
TMT1SYNC | none | 2 |
T1OSCEN | none | 3 |
T3SYNC | none | 2 |
TMR3CS | none | 1 |
TMR3ON | none | 0 |
BitTest | 2 | (<0> & (0x01 << <1>)) |
BIT_0 | none | 1 |
BIT_1 | none | 2 |
BIT_2 | none | 4 |
BIT_3 | none | 8 |
BIT_4 | none | 16 |
BIT_5 | none | 32 |
BIT_6 | none | 64 |
BIT_7 | none | 128 |
and | none | & |
ror | none | >> |
rol | none | << |
_SET | none | 1 |
_CLEAR | none | 0 |
_ALL | none | 255 |
adress_LED_IC3 | none | 0b11000100 |
adress_LED_IC4 | none | 0b11000010 |
adress_LED_IC5 | none | 0b11000110 |
adress_LED_IC6 | none | 0b11000000 |
BTFSC | 2 | (<0> & <1>) != 0 |
BitSet | 2 | (<0> |= (1<<<1>)) |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
BitNeg | 2 | (<0> ^= (1<<<1>)) |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
__PIC18F8720A__ | none | |
rtc_LIB | none | |
Output | none | 0 |
Input | none | 1 |
and | none | & |
or | none | | |
BitTest | 2 | (<0> & (0x01 << <1>)) |
BIT_0 | none | 1 |
BIT_1 | none | 2 |
BIT_2 | none | 4 |
BIT_3 | none | 8 |
BIT_4 | none | 16 |
BIT_5 | none | 32 |
BIT_6 | none | 64 |
BIT_7 | none | 128 |
and | none | & |
ror | none | >> |
rol | none | << |
BTFSC | 2 | (<0> & <1>) != 0 |
BitSet | 2 | (<0> |= (1<<<1>)) |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
BitNeg | 2 | (<0> ^= (1<<<1>)) |
_true | none | 1 |
_false | none | 0 |
AddressDS3231_read | none | 0b11010001 |
AddressDS3231_write | none | 0b11010000 |
AddressDS3231_temp_MSB | none | 0x11 |
AddressDS3231_temp_LSB | none | 0x12 |
_XTAL_FREQ | none | 30000000 |
_wt_speed_i2c_Masterx | none | 50000L |
ACKNOWLEDGE | none | 1 |
NOT_ACKNOWLEDGE | none | 0 |
MaskSeconds | none | 0b00001111 |
MaskSeconds_10 | none | 0b01110000 |
MaskMinutes | none | 0b00001111 |
MaskMinutes_10 | none | 0b01110000 |
MaskHour | none | 0b00001111 |
MaskHour_10 | none | 0b00010000 |
MaskAM_PM | none | 0b00100000 |
Mask_12_24 | none | 0b01000000 |
MaskClearSignTemp | none | 0b01111111 |
MaskClear76bit | none | 0b11111100 |
MaskClear76bitneg | none | 0b00000011 |
SQW_RATE_1 | none | 0 |
SQW_RATE_1K | none | 1 |
SQW_RATE_4K | none | 2 |
SQW_RATE_8K | none | 3 |
OUTPUT_SQW | none | 0 |
OUTPUT_INT | none | 1 |
and | none | & |
or | none | | |
tecka | none | 0x2e |
minus | none | 0x2d |
RST_RTC | none | PORTB |
_RB3 | none | 3 |
INT_RTC | none | RST_RTC |
_RB4 | none | 4 |
LATB_RTC | none | LATB |
tRTC | none | TRISB |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
AddressDS3231_write | none | 0b11010000 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
AddressDS3231_read | none | 0b11010001 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
ACKNOWLEDGE | none | 1 |
_HW | none | 1 |
NOT_ACKNOWLEDGE | none | 0 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
AddressDS3231_write | none | 0b11010000 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
_HW | none | 1 |
AddressDS3231_write | none | 0b11010000 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
_HW | none | 1 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint16_t | none | <\077435>uint16_t |
rol | none | << |
or | none | | |
ror | none | >> |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
or | none | | |
rol | none | << |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
or | none | | |
rol | none | << |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
or | none | | |
rol | none | << |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
uint8_t | none | <\077435>uint8_t |
minus | none | 0x2d |
tecka | none | 0x2e |
or | none | | |
or | none | | |
BitSet | 2 | (<0> |= (1<<<1>)) |
RST_RTC | none | PORTB |
PORTB | none | <\077435>PORTB |
_RB4 | none | 4 |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
LATB_RTC | none | LATB |
LATB | none | <\077435>LATB |
_RB4 | none | 4 |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
tRTC | none | TRISB |
TRISB | none | <\077435>TRISB |
_RB4 | none | 4 |
BitSet | 2 | (<0> |= (1<<<1>)) |
RST_RTC | none | PORTB |
PORTB | none | <\077435>PORTB |
_RB4 | none | 4 |
BitSet | 2 | (<0> |= (1<<<1>)) |
INT_RTC | none | RST_RTC |
RST_RTC | none | PORTB |
PORTB | none | <\077435>PORTB |
_RB3 | none | 3 |
BitSet | 2 | (<0> |= (1<<<1>)) |
LATB_RTC | none | LATB |
LATB | none | <\077435>LATB |
_RB3 | none | 3 |
BitSet | 2 | (<0> |= (1<<<1>)) |
tRTC | none | TRISB |
TRISB | none | <\077435>TRISB |
_RB3 | none | 3 |
BitSet | 2 | (<0> |= (1<<<1>)) |
RST_RTC | none | PORTB |
PORTB | none | <\077435>PORTB |
_RB4 | none | 4 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
BitClear | 2 | (<0> &= ~(1<<<1>)) |
RST_RTC | none | PORTB |
PORTB | none | <\077435>PORTB |
_RB4 | none | 4 |
__delay_ms | 1 | _delay((unsigned long)((<0>)*(_XTAL_FREQ/4000.0))) |
_XTAL_FREQ | none | 30000000 |
BitSet | 2 | (<0> |= (1<<<1>)) |
RST_RTC | none | PORTB |
PORTB | none | <\077435>PORTB |
_RB4 | none | 4 |
and | none | & |
MaskSeconds | none | 0b00001111 |
and | none | & |
MaskSeconds_10 | none | 0b01110000 |
and | none | & |
MaskMinutes | none | 0b00001111 |
and | none | & |
MaskMinutes_10 | none | 0b01110000 |
and | none | & |
MaskHour | none | 0b00001111 |
and | none | & |
MaskHour_10 | none | 0b00010000 |
and | none | & |
MaskAM_PM | none | 0b00100000 |
and | none | & |
Mask_12_24 | none | 0b01000000 |