Příklady v jazyce VHDL

entity scitac is
 port (a, b: in std_logic_vector(7 downto 0);
       cin: in std_logic;
       cout: out std_logic;
       sum: out std_logic_vector (7 downto 0));
end scitac;
architecture scitac1 of scitac is
begin
 process (cin, a, b)
 variable temp : std_logic_vector (8 downto 0);
 begin
  temp := ('0' & a) + ('0' & b) + ("00000000"& cin);
  cout <= temp(8) after 1 ns;
  sum <= temp(7 downto 0) after 1 ns;
 end process;
end scitac1;

entity alu is
 port (opcode : in bit_vector(2 downto 0);
       a, b, cin, clock : in bit;
       s, cout : out bit);
end alu;
architecture alu1 of alu is
begin
 process begin
  wait until clock'event and clock='1';
  case opcode is
   when "000" => s <= '0'; -- vynulovat, s <= 0
   when "001" => s <= not(a); -- negace, s <= /a
   when "010" => s <= a xor cin; -- increment, s <= a+cin
              cout <= a and cin;
   when "011" => s <= not(a xor cin); -- negate, s <= /a + cin
              cout <= a and cin;cout <= (not(a)) and cin;
   when "100" => s <= b; -- prenos b, s <= b
   when "101" => s <= a xor b; -- XOR, a XOR b
   when "110" => s <= (a xor b) xor cin; -- Add, a + b + cin
              cout <= a and cin;cout <= (a and cin) or (b and (a xor cin));
   when "111" => s <= a xor (not(b)) xor cin; -- Subtract, a + /b + cin
         cout <= a and cin;cout <= (a and cin) or ((not(b)) and (a xor cin));
   when others =>
  end case;
 end process;
end alu1;

entity alu is
 port (opcode : in bit_vector(2 downto 0);
       bin : in bit_vector(3 downto 0);
       load : in bit;
       clock : in bit;
       areg : buffer bit_vector(3 downto 0);
       breg : buffer bit_vector(3 downto 0);
       carry : buffer bit);
end alu;
architecture alu2 of alu is
begin
 process
  variable a : bit;
  variable b : bit;
  variable cin : bit;
  variable s : bit;
  variable cout : bit;
  begin
  wait until clock'event and clock = '1';
  if (load = '1') then
   breg <= bin;
   areg <= "0000";
  else
   a := areg(0);
   areg(0) <= areg(1);
   areg(1) <= areg(2);
   areg(2) <= areg(3);
   b := breg(0);
   breg(0) <= breg(1);
   breg(1) <= breg(2);
   breg(2) <= breg(3);
   breg(3) <= b;
   cin := carry;
   case opcode is
    when "000" => s := '0'; -- clear, s <= 0
    when "001" => s := not(a); -- compliment, s <= /a
    when "010" => s := a xor cin; -- increment, s <= a+cin
               cout := a and cin;
    when "011" => s := not(a xor cin); -- negate, s <= /a + cin
               cout := (not(a)) and cin;
    when "100" => s := b; -- transfer b, s <= b
    when "101" => s := a xor b; -- XOR, a XOR b
    when "110" => s := (a xor b) xor cin; -- Add, a + b + cin
               cout := (a and cin) or (b and (a xor cin));
    when "111" => s := a xor (not(b)) xor cin; -- Subtract, a + /b + cin
               cout := (a and cin) or ((not(b)) and (a xor cin));
    when others =>
   end case;
   areg(3) <= s;
   carry <= cout;
  end if;
 end process;
end alu2;

--hacesoft 24.7.2005
--prochazka.zde.cz
--posuvné matematické operace
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity posuny is
 Port ( clk : in std_logic;      -- vstup hodinoveho pulzu.
   prikaz : in signed(3 downto 0); -- přikaz co se ma provest.
   Vystup : out signed(7 downto 0)); -- vystup
end posuny;

architecture behavioral of posuny is
signal Vstup: signed(7 downto 0);
begin

process (clk) begin
 if clk='1' and clk'event then
   case prikaz is
     when "0000" =>
       Vstup <= "11001001"; --201
     when "0001" =>
       Vstup <= Vstup sll 1;
     when "0010" =>
       Vstup <= Vstup sll 2;
     when "0011" =>
       Vstup <= Vstup srl 1;
     when "0100" =>
       Vstup <= Vstup srl 2;
     when "0101" =>
       Vstup <= Vstup rol 1;
     when "0110" =>
       Vstup <= Vstup rol 2;
     when "0111" =>
       Vstup <= Vstup ror 1;
     when "1000" =>
       Vstup <= Vstup ror 2;
     when "1001" =>
       Vstup <= Vstup + 1;
     when "1010" =>
       Vstup <= Vstup - 1;
     when "1011" =>
       Vstup <= Vstup / 1;
     when "1100" =>
       Vstup <= "11111111";
     when

entity comp is
 port (a, b: in bit_vector;
       y: out bit);
end comp;
architecture comp1 of comp is
begin
 process (a, b) begin
  if a <= b then y <= '1';
   else y <= '0';
  end if;
 end process;
end comp1;

entity RS is
 port (reset, set: in std_logic;
       y : out std_logic);
end RS;
architecture rtl of RS is
begin
 process (reset, set) begin
  if (reset = '0') then
   y <= '0';
  elsif (set = '0') then
   y <= '1';
  end if;
 end process;
end rtl;

entity d_latch is
 port (enable, data: in std_logic;
       y: out std_logic);
end d_latch;
architecture rtl of d_latch is
begin
 process (enable, data) begin
  if (enable = '1') then
   y <= data;
  end if;
 end process;
end rtl;

entity d_latch_enp is
 port (enable, data, data1 : in std_logic;
       q : out std_logic);
end d_latch_enp;
architecture rtl of d_latch_enp is
begin
 process (enable, data, data1) begin
  if ((enable) = '1') then
   q <= data and data1 ;
  end if;
 end process;
end rtl;

entity d_latch_en is
 port (enable, gate, d : in std_logic;
       q : out std_logic);
end d_latch_en;
architecture rtl of d_latch_en is
begin
 process (enable, gate, d) begin
  if ((enable and gate) = '1') then
   q <= d;
  end if;
 end process;
end rtl;

entity d_latch_async_reset is
 port (enable, data, reset : in std_logic;
       q : out std_logic);
end d_latch_async_reset;
architecture rtl of d_latch_async_reset is
begin
 process (enable, data, reset) begin
  if (reset ='1') then
   q <='0';
  elsif (enable ='1') then
   q <= data;
  end if;
 end process;
end rtl;

entity d_latch_async_set is
 port (enable, data, set: instd_logic;
       q: outstd_logic);
end d_latch_async_set;
architecture rtl of d_latch_async_set is
begin
 process (enable, data, set) begin
  if (set ='0') then
   q <='1';
  elsif (enable ='1') then
   q <= data;
  end if;
 end process;
end rtl;

entity d_latch_async is
 port (enable, data, reset, set:instd_logic;
       q:outstd_logic);
end d_latch_async;
architecture rtl of d_latch_async is
begin
 process (enable, data, reset, set) begin
  if (set ='0') then
   q <= '1';
  elsif (reset ='0') then
   q <= '0';
  elsif ( enable ='1') then
   q <= data;
  end if;
 end process;
end rtl;

entity dff_pos is
 port (data, clk : in std_logic;
       q : out std_logic);
end dff_pos;
architecture rtl of dff_pos is
begin
 process (clk) begin
  if (clk'event and clk = '1') then
   q <= data;
  end if;
 end process;
end rtl;

entity dff_neg is
 port (data, clk : in std_logic;
       q : out std_logic);
end dff_neg;
architecture rtl of dff_neg is
begin
 process (clk) begin
  if (clk'event and clk = '0') then
   q <= data;
  end if;
 end process;
end rtl;

entity dff_async_reset_orig is
 port (data, clk, reset : in std_logic;
       q : out std_logic);
end dff_async_reset_orig;
architecture rtl of dff_async_reset_orig is
begin
 process (clk, reset) begin
  if (reset = '1') then
   q <= '0';
  elsif (clk'event and clk = '1') then
   q <= data;
  end if;
 end process;
end rtl;

entity dff_async_set_orig is
 port (data, clk, set : in std_logic;
       q : out std_logic);
end dff_async_set_orig;
architecture rtl of dff_async_set_orig is
begin
 process (clk, set) begin
  if (set ='0') then
   q <='1';
  elsif (clk'event and clk = '1') then
   q <= data;
  end if;
 end process;
end rtl;

entity dff_async is
 port (data, clk, reset, set: in std_logic;
       q: out std_logic);
end dff_async;
architecture rtl of dff_async is
begin
 process (clk, reset, set) begin
  if (reset = '1') then
   q = '0';
  elsif (set = '1') then
   q = '1';
  elsif (clk'event and clk = '1') then
   q = data;
  end if;
 end process;
end rtl;

entity dff_sync_reset is
 port (data, clk, reset : in std_logic;
       q : out std_logic);
end dff_sync_reset;
architecture rtl of dff_sync_reset is
begin
 process (clk) begin
  if (clk'event and clk = '1') then
   if (reset = '0') then
    q <= '0';
   else q <= data;
   end if;
  end if;
 end process;
end rtl;

entity dff_sync_set is
 port (data, clk, set : in std_logic;
       q : out std_logic);
end dff_sync_set;
architecture rtl of dff_sync_set is
begin
 process (clk) begin
  if (clk'event and clk = '1') then
   if (set = '1') then
    q <= '1';
   else q <= data;
   end if;
  end if;
 end process;
end rtl;

entity dff_a_s_load is
 port(sload, aload, adata, sdata, clk : in std_logic;
       q : out std_logic);
end dff_a_s_load;
architecture rtl of dff_a_s_load is
begin
 process (clk, aload) begin
  if (aload = '1') then
   q <= adata;
  elsif (clk'event and clk = '1') then
   if (sload = '1') then
    q <= sdata;
   end if;
  end if;
 end process;
end rtl;

entity dff_arsl_sl is
 port (reset, set, aload, sload, clk :in std_logic;
       adata,sdata : in std_logic_vector (3 downto 0);
       q : out std_logic_vector (3 downto 0));
end dff_arsl_sl;
architecture rtl of dff_arsl_sl is
begin
 process (clk, reset, set, aload) begin
  if (reset = '1') then
   q <= ("0000");
  elsif (set = '1') then
   q <= "1111";
  elsif (aload = '1') then
   q <= adata;
  elsif (clk'event and clk = '1') then
   if (sload = '1') then
    q <= sdata;
   end if;
  end if;
 end process;
end rtl;

entity JK is
 port (J: in std_logic;
       K, CLK : in std_logic;
       Q_out : out std_logic);
end JK;
architecture rtl of JK is
 signal Q : std_logic;
begin
 process
  variable JK : std_logic_vector (1 downto 0);
 begin
  wait until (CLK'event and CLK = '1');
  JK := (J & K);
  case JK is
   when "01" => Q <= '0';
   when "10" => Q <= '1'
   when "11" => Q <= not (Q);
   when "00" => Q <= Q;
   when others=> Q <= 'X';
  end case;
 end process;
 Q_out <= Q;
end rtl;

entity jk_async_sr is
 port (RESET, SET, J, K, CLK : in std_logic;
       Q_out : out std_logic );
end jk_async_sr;
architecture rtl of jk_async_sr is
 attribute sync_set_reset of J, K : signal is "true";
 attribute one_hot of RESET ,SET : signal is "true";
 signal Q : std_logic;
begin
 process (CLK, RESET, SET)
  variable JK : std_logic_vector (1 downto 0);
 begin
  if (RESET = '1') then
   Q <= '0';
  elsif (SET = '1') then
   Q <= '1';
  elsif (clk'event and CLK = '1') then
   JK := (J & K);
   case JK is
    when "01" => Q <= '0';
    when "10" => Q <= '1';
    when "11" => Q <= not(Q);
    when "00" => Q <= Q;
    when others => Q <= 'X';
   end case;
  end if;
  Q_out <= Q;
 end process;
end rtl;

entity transport1 is
 Port (DIR: in std_logic;
       A : buffer std_logic_vector(7 downto 0);
       B : buffer std_logic_vector(7 downto 0));
end transport1;
architecture behavioral of transport1 is
begin
 process (DIR) begin
 -- Signál DIR určuje tok dat.
  if DIR = '0' THEN A <= B;
   else A <= "ZZZZZZZZ"; end if;
  if DIR = '1' THEN B <= A;
  else B <= "ZZZZZZZZ"; end if;
 end process;
end behavioral;

entity t_async_reset is
 port (RESET, CLK : in std_logic;
       Q: out std_logic);
end t_async_reset;
architecture rtl of t_async_reset is
 signal tmp_q : std_logic;
begin
 process (CLK, RESET) begin
  if (RESET = '1') then
   tmp_q <= '0';
  elsif (CLK'event and CLK = '0') then
   tmp_q <= not (tmp_q);
  end if;
 end process;
 Q <= tmp_q;
end rtl;

entity t_async_set is
 port(SET, CLK : in std_logic;
       Q : out std_logic);
end t_async_set;
architecture rtl of t_async_set is
 signal tmp_q : std_logic;
begin
 process (CLK, SET) begin
  if (SET ='1') then
   tmp_q <='1';
  elsif (CLK'event and CLK ='1')
   then tmp_q <= not (tmp_q);
  end if;
 end process;
 Q <= tmp_q;
end rtl;

entity t_async_en_r is
 port (RESET, TOGGLE, CLK : in std_logic;
       Q : out std_logic);
end t_async_en_r;
architecture rtl of t_async_en_r is
 signal tmp_q : std_logic;
begin
 process (CLK, RESET) begin
  if (RESET ='1') then
   tmp_q <='0';
  elsif (CLK'event and CLK ='1') then
   if (TOGGLE ='1') then
    tmp_q <= not (tmp_q);
   end if;
  end if;
 end process;
 Q <= tmp_q;
end rtl;

entity multi_attr is
 port (data1, data2, clk, reset, sload : in std_logic;
       q1, q2 : out std_logic );
end multi_attr;
architecture rtl of multi_attr is
 attribute async_set_reset_local of infer_async : label is "reset";
 attribute sync_set_reset_local of infer_sync : label is "reset";
begin
infer_sync :
 process (clk) begin
  if (clk'event and clk ='1') then
   if ( reset ='0') then
    q1 <='0';
   elsif (sload ='1') then
    q1 <= data1;
   end if;
  end if;
 end process infer_sync;
infer_async :
 process (clk, reset) begin
  if ( reset ='0') then
   q2 <= '0';
  elsif (clk'event and clk ='1') then
   if (sload ='1') then
    q2 <= data2;
   end if;
  end if;
 end process infer_async;
end rtl;

entity mslatch is
 port (mclk, sck, data : in STD_LOGIC;
       q : out STD_LOGIC );
end mslatch;
architecture rtl of mslatch is
begin
   -- pragma dc_script_begin
   -- set_signal_type "clocked_on_also" sck
   -- pragma dc_script_end
 process(mclk, data) begin
  if (mclk'event and mclk = '1') then
   q <= data;
  end if;
 end process;
end rtl;

entity mslatcH4 is
 port (mck1, sck1, data1, mck2, sck2, data2 : in STD_LOGIC;
       q1, q2 : out STD_LOGIC );
end mslatcH4;
architecture rtl of mslatcH4 is
begin
   -- pragma dc_script_begin
   -- set_signal_type "clocked_on_also" sck1 -associated_clock mck1
   -- set_signal_type "clocked_on_also" sck2 -associated_clock mck2
   -- pragma dc_script_end
infer1:
 process(mck1, data1) begin
  if (mck1'event and mck1 ='1') then
   q1 <= data1;
  end if;
end process infer1;
infer2:
 process(mck2, data2) begin
  if (mck2'event and mck2 ='1') then
   q2 <= data2;
  end if;
 end process infer2;
end rtl;